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xilinx_usb_drivers_win10_x64
说明： win10的xilinx usb驱动，较新版本(Xilinx USB driver for win10, newer version)
- 2021-03-11 17:09:26下载
- 积分：1
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FPGA
基于FPGA的数字系统设计,包含原理、工程应用和案例。(FPGA-based digital system design, including theory, engineering applications and cases.)
- 2010-10-12 21:34:00下载
- 积分：1
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FIR
FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)
- 2021-04-15 11:08:54下载
- 积分：1
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vhdl programming from beginner level
vhdl programming from beginner level
- 2022-02-04 01:13:09下载
- 积分：1
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adc_dac
ADC-DAC transmittion works thru SPI on 25 MHZ. Used for some student project on Xilinx sprtan3a FPGA
- 2016-12-01 19:44:33下载
- 积分：1
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project_first
basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)
- 2019-06-18 10:37:53下载
- 积分：1
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Radar-on-FPGA
主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。(Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given)
- 2012-08-11 17:51:55下载
- 积分：1
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FPGA-powe-analysis-tool-EPE
FPGA功耗分析工具EPE用于分析FPGA系统的功耗(FPGA power analysis tools EPE is used to analyze the power consumption of the FPGA system)
- 2012-11-19 17:08:00下载
- 积分：1
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1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES...
1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-08-08 19:22:01下载
- 积分：1
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imports
说明： displayport 参考设计，可以对比自己工程做验证，另有参考设计XAPP1178未找到，采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)
- 2021-01-11 16:58:50下载
- 积分：1
