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Hardware-CNN-master
说明： Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分：1
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十六进制7Segment时钟
十六进制计数器递增 ALTERA FPGA 板 7 段显示器上的每一秒。
- 2022-07-13 21:46:37下载
- 积分：1
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reader
实现verilog读写txt文件，从sut.txt从读取数据，进行操作后，写入out.txt(Realize verilog read and write txt file)
- 2020-11-15 21:29:41下载
- 积分：1
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iir
八阶巴特沃兹iir数字滤波器，四个二阶节，verilog代码实现，多路分时复用(batterworth，iir，8order，four second order section)
- 2016-01-27 19:49:47下载
- 积分：1
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ethernet_mii_udp_1
说明： Verilog开发的，MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)
- 2020-03-20 16:19:21下载
- 积分：1
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希尔伯特变换是通信系统中的一个重要组成部分，如：
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented.
The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940).
The design is fully pipelined for maximum throughput.
- 2023-02-02 09:20:04下载
- 积分：1
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一个用vhdl硬件描述语言实现的一个比较简单的除法器
一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl
- 2022-05-15 11:56:12下载
- 积分：1
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rom_fft
采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)
- 2013-09-14 20:59:03下载
- 积分：1
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claa
vhdl code for carry lookahead addder
- 2014-02-05 00:26:26下载
- 积分：1
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msk_mod_demod
该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)
- 2013-10-14 23:02:39下载
- 积分：1
