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DDS FPGA开发下的verilog源代码
DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器(DDS_AD9854_for FPGA, verilog source code, signal generator.)
- 2013-01-14 00:13:36下载
- 积分：1
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AHB-answers
这个文档回答了很多关于AHB总线在使用上经常遇到的问题(this doc gives a lot of answers for using AHB bus when doing design)
- 2020-10-21 12:17:24下载
- 积分：1
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NAND_flash_verilog_vhdl
很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference
This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host
end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address
bus, data bus, error status signal, control and handshake signals for the user......)
- 2021-03-08 22:59:28下载
- 积分：1
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7-segment
VHDL Design of BCD to 7-segment decoder
using PROM
- 2009-05-04 02:44:02下载
- 积分：1
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用于视频图像编码的8×8DCT变换，可用于MPEG4.H263等VHDL编程
用于视频图像编码的8×8DCT变换，可用于MPEG4.H263等VHDL编程-For video images encoded 8 × 8DCT transform, can be used to MPEG4.H263 such as VHDL Programming
- 2022-03-17 09:22:10下载
- 积分：1
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3g-sdi
3g-sdi驱动器，用于全高清视频FPGA解决方案(3g-sdi driver)
- 2013-08-06 21:59:37下载
- 积分：1
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the program two integers and the sum of squared output
本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output
- 2023-08-09 04:10:02下载
- 积分：1
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configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design do...
可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
- 2022-01-26 00:23:00下载
- 积分：1
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PN_GEN
说明： 一个PN序列发生器，大M序列，供参考学习，(A PN sequence generator, the M series, for reference study,)
- 2008-10-20 13:46:45下载
- 积分：1
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SDI_test
stratixIVGX，芯片4sgx230es，SDI测试完整工程，实现SDI的收发(stratixIVGX，SDI Receive and Transmit)
- 2011-12-12 14:57:53下载
- 积分：1
