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mypro_synfifo
基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)
- 2020-09-22 01:27:56下载
- 积分：1
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lovesh
NN CONTROLLER FOR UPQC
- 2012-11-12 14:01:31下载
- 积分：1
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project_comfinal
说明： it can add two numbers and shows the answer
- 2019-05-28 19:16:02下载
- 积分：1
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traffic
说明： 模拟交通灯
verilog CPLD
EPM1270
源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)
- 2008-10-30 23:12:20下载
- 积分：1
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DE2_Default
基于DE2开发板的VGA显示模块，仅供大家参考(DE2 development board based on the VGA display module, for your reference)
- 2008-07-21 16:12:32下载
- 积分：1
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dekoder
dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL
- 2009-06-19 22:13:52下载
- 积分：1
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chap12
《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)
- 2007-07-01 16:33:31下载
- 积分：1
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55593397xapp592
GTH 和SMPTE IP 实现 SDI视频接收(SDI Video Receiving Based on GTH and SMPTE IP)
- 2019-02-18 16:09:33下载
- 积分：1
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dds正弦发生器代码
讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果(described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output)
- 2005-04-21 08:04:15下载
- 积分：1
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xapp1251
说明： 1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. INSTALLATION AND OPERATING INSTRUCTIONS
6. SUPPORT
- 2020-11-07 09:49:49下载
- 积分：1
