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LCD_1602
说明： 以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分：1
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jjiaotongdeng
实现fpga上交通灯的设计，可以在开发板上实现红绿灯(Design of traffic lights on FPGA)
- 2018-08-28 16:42:27下载
- 积分：1
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Dice_game
VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.
- 2011-02-22 22:07:59下载
- 积分：1
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xilinx pcie verilog code
用于学习和研究pcie硬件
有完整的仿真testbench及xilinx pcie softcore
- 2023-06-23 01:35:06下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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immediate_divide_module
用组合逻辑实现循环除法器。稳定、安全、可靠。(Combinational logic loop divider. Stable, secure, and reliable.)
- 2012-08-30 09:08:04下载
- 积分：1
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sqr
VHDL CODE FOR SQUARE WAVE GENERATOR
- 2014-01-22 17:14:20下载
- 积分：1
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Fast_median_filter
说明： FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)
- 2019-06-01 21:23:25下载
- 积分：1
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traffic_lights
交通灯控制器控制红（r）、绿（g）、黄（y）三种不同颜色的交通灯，这三种不同颜色灯的亮、灭分别由三个定时器（timer1、timer2、timer3）控制；
当某个定时器工作时，它所控制的交通灯亮，直到设定的定时时间到（该定时器状态由’0’变’1’），交通灯跳转到另一种状态；
clk是脉冲控制端（图中未标出）；reset是异步复位端，复位状态为红色交通灯亮；
输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。
( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights output terminal r, g, y represent the three colors of traffic lights bright, the off state.)
- 2020-12-19 15:09:10下载
- 积分：1
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FPGA做从设备的IIC逻辑
用逻辑实现iic协议，其中fpga端作为从设备，接收主设备发送过来的信号，并解析。由于是是作为从设备，因此，也不需要发送对端的IIC地址，对外就是SDA和SCL这2根信号线
- 2022-04-08 08:36:38下载
- 积分：1
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