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                        Booth2_final
                        
                          该文件是booth乘法器的verilog源代码,经过最终的仿真,可以直接运行(This file is booth multiplier verilog code, after the final simulation, can be directly run)                         
                            - 2015-05-08 09:29:56下载
- 积分:1
 
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                        子带编码,在Verilog SPIHT算法
                        
                          文件包含                         
                            - 2022-01-25 21:51:55下载
- 积分:1
 
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                        FPGA——IP_RAM实验
                        
                          说明:  FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
	input	[9:0]  address;
	input	  clock;
	input	[7:0]  data;
	input	  wren;                 //置1则写入
	output	[7:0]  q;
LNXmode:控制LEDC显示
	1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
	     8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)                         
                            - 2020-06-22 04:20:02下载
- 积分:1
 
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                        LDPC最小和译码算法verilog代码
                        
                          此部分verilog代码为ldpc的最小和译码算法verilog源代码。verilog源代码适用于Xilinx和altera开发环境。                         
                            - 2022-02-05 17:42:10下载
- 积分:1
 
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                        qiangdaqi
                        
                          本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)                         
                            - 2013-10-30 14:48:21下载
- 积分:1
 
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                        CycloneII_NiosII_2C35_Rev02_DB_SCH
                        
                          说明:  nios开发板电路图CycloneII_NiosII_2C35_Rev02_DB_SCH.zip(nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip)                         
                            - 2010-03-28 20:50:27下载
- 积分:1
 
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                        VHDL
                        
                          用VHDL语言实现一Mealy型时序电路,并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)                         
                            - 2014-03-20 14:44:28下载
- 积分:1
 
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                        Verilog--image-sample
                        
                          基于Verilog的图像采集、处理和存储程序,初学者参考,高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)                         
                            - 2021-04-16 11:48:54下载
- 积分:1
 
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                        tanchishe-QuartusII
                        
                          VGA显示FPGA实现的VHDL语言的贪吃蛇游戏设计
本设计分为6个模块主要是扫描模块 VGA现实和控制模块 游戏设计的模块 电源模块等
用QUARTUS2仿真运行(VGA display FPGA VHDL language to realize the Snake game design 
The design is divided into six modules mainly scanning module VGA module power module and control module reality game design, etc. 
Simulation run with QUARTUS2)                         
                            - 2020-11-06 10:09:50下载
- 积分:1
 
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                        beep_interface
                        
                          这些代码为 对于基本的FPGA使用模块beep进行了例化  在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)                         
                            - 2013-05-05 21:07:18下载
- 积分:1