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mp3_player
Altera board
Mp3 project
- 2011-12-27 15:04:02下载
- 积分:1
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e1framer
E1 deframmer and Frammer.
- 2013-02-25 19:43:35下载
- 积分:1
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IC设计基础
说明: 一本很经典的IC设计中文入门书籍,由任艳颖,王彬编著,翻印几百万册(A very classic introduction to Chinese in IC design book, compiled by Ren Yanying and Wang Bin, reprinted millions of copies)
- 2020-06-23 22:20:02下载
- 积分:1
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Hardware-CNN-master
Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分:1
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shuzizhongsheji
有用的数字钟设计文档,有秒表、闹钟等模块,希望对大家有用!(JUST LEARN FROM IT!!ENJOY!)
- 2013-07-18 11:02:24下载
- 积分:1
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基于fpga的SPI接口实现
本工程是基于Altera Cyclone系列的FPGA来实现的SPI接口,使用Verilog代码编写,能够进行 8位、 16位 、 32位数据传输的可选操作。
- 2023-04-02 17:15:05下载
- 积分:1
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5_lcd_ST7565P_12864
液晶ST7565P_12864驱动,实现打点成图。(LCD ST7565P_12864 drive, dot mapping.)
- 2012-04-04 20:01:42下载
- 积分:1
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fir_verilog_matlab
本设计是基于FPGA的一个FIR低通滤波器设计,要求使用Verilog语言编写滤波器模块,通过编译和综合,并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)
- 2014-03-21 09:58:41下载
- 积分:1
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24小时计时时钟
说明: 实现24小时计时,因为位数不够,这里是12进位,可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分:1
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24x24-booth
可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)
- 2011-06-09 17:59:26下载
- 积分:1