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Stumper.cpp
Convert Roman numerals to integers
- 2012-12-05 03:59:59下载
- 积分:1
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SPI_test
说明: 用FPGA于32进行SPI单向通信,FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)
- 2020-06-18 10:40:02下载
- 积分:1
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32位除法器verilog设计
使用了不恢复余数循环移位减法来实现除法功能,在硬件资源与除法周期之间取了折中,32位除法要进行32次移位减法,使用了5个64位的寄存器,一个周期做4次移位减法,8个周期完成一次除法操作。设计全部用verilog实现。详细算法见图:
- 2023-01-08 07:15:02下载
- 积分:1
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4*4键盘扫描程序,以上机验证可用
该程序实现了4*4键盘的扫描功能,并且在xilinx basys2实验板上验证可以运行,在压缩包内是完整的程序供大家参考
- 2022-06-14 14:25:01下载
- 积分:1
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DCT_IDCT
H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码(H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code)
- 2011-06-11 07:08:30下载
- 积分:1
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FPGA_GFP
基于FPGA的GFP(通用成帧协议)封装数据成帧的实现。(FPGA-based GFP (Generic Framing Protocol) encapsulated data Framing realized.)
- 2007-07-20 15:07:59下载
- 积分:1
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基于verilog的出租车付费系统
基于verilog的出租车付费系统 带验证模块
- 2022-04-18 19:22:44下载
- 积分:1
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Project7_5
基于fpga状态机的交通灯设计,亮灯时间自己修改,程序简单易懂。(Traffic light design based on FPGA state machine, light time self-modifying, the program is simple and easy to understand.)
- 2020-06-18 04:00:01下载
- 积分:1
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CAN协议控制器的Verilog实现
说明: 基于FPGA的CAN总线控制器,VERILOGHDL源代码,Q2仿真实现。可用。(FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.)
- 2020-11-26 15:29:31下载
- 积分:1
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mul24x24
24位x24位的乘法器
十分详细24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器(24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier)
- 2009-06-08 10:00:58下载
- 积分:1