-
FPGA 64位除法器 verilog
用verilog语言实现的除法器，实现方式为移位减
- 2023-09-02 08:35:03下载
- 积分：1
-
QPSK_demod
说明： QPSK的解调程序，采用Verilog编写而成(QPSK demodulation program, written by Verilog)
- 2020-02-29 19:51:38下载
- 积分：1
-
delta-sigma
实现了MASH111功能，输入位数可编程(MASH 1-1-1, delta-sigma , input bits are programmable)
- 2021-04-20 23:18:50下载
- 积分：1
-
NIOSII-Qsys_v1.3.1
黑金刚FPGA开发板使用说明文档，讲诉了NIOS和Qsys的详细开发步奏，值得学习。(KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.)
- 2015-03-25 13:42:03下载
- 积分：1
-
单周期cpu
说明： 该文件包含了实现单周期cpu的全部代码以及实验报告，包括仿真波形以及烧板过程(This file contains all the codes and experimental reports of realizing single cycle CPU, including simulation waveform and download process)
- 2019-12-14 20:55:42下载
- 积分：1
-
LMS
用verilog编写的lms算法。可实现自适应滤波功能(Lms algorithm written in verilog. Adaptive filtering can be achieved)
- 2021-05-15 11:30:02下载
- 积分：1
-
新建文件夹 (3)
说明： 对温湿度采集芯片进行配置并且把读到的温度数据显示到数码管上(The temperature and humidity acquisition chip is configured and the temperature data read is displayed on the nixie tube)
- 2020-06-30 22:23:15下载
- 积分：1
-
taxi
利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)
- 2011-08-30 08:18:51下载
- 积分：1
-
syn_rd_wr_fifo
该代码实现了FPGA对USB芯片68013的读写，语言是VERLOD，试验通过。(The code to achieve the FPGA read and write 68013 on the USB chip, the language is VERLOD, through the test.
)
- 2015-05-02 14:34:16下载
- 积分：1
-
ISE
设计一4位比较器,画出门级电路图,用verilog语言完成设计。
(Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )
- 2015-12-11 21:16:12下载
- 积分：1
