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Xilinx 的DDR SDRAM控制器,用Verilog HDL描述

于 2022-08-12 发布 文件大小:463.11 kB
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Xilinx 的DDR SDRAM控制器,用Verilog HDL描述- A DDR SDRAM contraller sample descripte in Verilog HDL ,base on Xilinx FPGA

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