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electrical lock
一个用Verilog写的电子锁工程,带testbench。(An electronic lock project written in Verilog with testbench.)
- 2020-06-30 05:00:01下载
- 积分:1
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HB1
半带滤波器,用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)
- 2020-12-23 10:29:06下载
- 积分:1
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al422b
AL422B,FPGA写的控制时序。XIWANGDUIDAJIAYOUYONG(AL422B,timing of AL422b.)
- 2014-04-17 21:41:09下载
- 积分:1
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EDanDanAssistg
蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ,经测试
(Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)
- 2012-09-10 00:33:07下载
- 积分:1
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AD5791_spi
该代码为VHDL语言描述的AD579 SPI通讯程序,包括一些代码注解。(Thisis a SPI communication promgram of AD5791 designed with VHDL which compared with some discreption.)
- 2021-04-20 14:28:50下载
- 积分:1
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DDS_signal_genarator
这是一个利用verilog语言编写的信号发生器的例子,值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)
- 2013-12-23 10:12:52下载
- 积分:1
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基于verilog的1588V2协议的fpga实现
基于verilog的1588V2协议的fpga实现,目前项目通用代码,供大家参考(Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference)
- 2021-04-26 10:58:46下载
- 积分:1
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SVPWM_method
给出了SVPWM算法的详细FPGA实现方法!(A detailed FPGA SVPWM algorithm to achieve the method!)
- 2017-04-05 13:43:14下载
- 积分:1
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用Verilog HDL实现的uart通用串口通信程序,已经验证成功
在ISE下开发的通用串口通信程序,使用的编程语言是Verilog HDL语言,采用了fifo,已经进行实验验证通过,适合Verilog初学者,欢迎交流学习。
- 2022-07-10 18:29:55下载
- 积分:1
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mypro_synfifo
基于IP核RAM的同步fifo设计,工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)
- 2020-09-22 01:27:56下载
- 积分:1