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9850sin_function
ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)
- 2013-08-27 15:13:29下载
- 积分:1
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qiangdaqi
本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)
- 2013-10-30 14:48:21下载
- 积分:1
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y210
三八译码器,四位加法器,EDA实验,用verilog编写(EDA experiment with verilog language)
- 2017-10-30 20:14:30下载
- 积分:1
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DEMO_CAM_LCD
实现了从摄像头读取数据到液晶的显示,利用了cycloneV 和康欣的开发板资源(It realizes the display of reading data from camera to liquid crystal.)
- 2019-07-05 15:25:36下载
- 积分:1
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Muliplexer
说明: Multiplexer 4 to 1 on Modelsim
- 2020-10-14 13:56:09下载
- 积分:1
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include UART port of VERILOG source, the program tested in FPGA, as chip design,...
包含UART口的VERILOG源程序,该程序在FPGA上验证通过,可作为芯片设计,或FPGA设计的一个完整IP核,硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
- 2022-06-01 13:44:15下载
- 积分:1
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rs-codec-8-16
RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)
- 2021-04-28 15:58:44下载
- 积分:1
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RISC-V-Reader-Chinese-v2p1
说明: RISC-V 芯片设计规范,很有参考价值,开源芯片设计必备参考资料,希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)
- 2020-07-01 23:00:02下载
- 积分:1
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GFverilog-hdl
伽罗华域的乘法器的设计,使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)
- 2011-05-01 13:19:22下载
- 积分:1
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crc8
8位crc的verilog设计 通过仿真综合验证并已应用在工程里面
(verilog of 8bit error checkout )
- 2021-03-01 11:09:34下载
- 积分:1