-
shizhong
VHDL写时钟,分频模块什么,实现计时。定点报时,定点闹钟,显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分:1
-
adder4
四位加法器 数码管显示 组合电路 verilog(adder4 smg display combitional circuit verilog)
- 2013-02-28 09:56:46下载
- 积分:1
-
I2S
SMT32F4 i2s 全双工配置,自己测试OK的,大家可以看看(SMT32F4 i2s 全双工配置)
- 2021-03-06 22:29:30下载
- 积分:1
-
basic_cpu_mano_ise_vhdl
morris mano basic vhdl code in ise
- 2014-01-13 05:52:01下载
- 积分:1
-
Ping_pong_Sparten3e-master
说明: FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)
- 2019-05-06 20:22:13下载
- 积分:1
-
BCH_EncDec_Matlab
bch编解码的完整版,本人已经做过fpga实现,就是按照该程序为原型,绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)
- 2011-10-27 21:55:11下载
- 积分:1
-
M_M
此为数学形态滤波器消燥的代码,用于一维信号,涉及一个具体的例子,需要的话可以自己修改,修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)
- 2013-08-29 21:36:37下载
- 积分:1
-
Chip_hardware_description_language_related_program
硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)
- 2010-07-28 07:53:40下载
- 积分:1
-
tlk2711test
用verilog语言实现了tlk2711serdes芯片的高速串行功能,包含工程与仿真文件,亲测可用(Using Verilog language to achieve a high-speed serial tlk2711serdes chip function, including the project and the simulation file, pro test available)
- 2020-12-29 23:39:00下载
- 积分:1
-
suzimiaobiao
数字秒表的实现,我还写个具体的过程要求等,(there is function of clock,it very useful)
- 2011-09-20 14:28:30下载
- 积分:1