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Verilog的135个经典设计实例.使你工作使用学习中，会有很大帮助，各种典型案例(135 classic Verilog design examples. Make your work with the study, will be of great help, of various typical cases
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- 2014-03-19 10:55:14下载
- 积分：1
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EncoderUsingif
encoder using else if statement
- 2015-05-21 13:41:00下载
- 积分：1
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24小时计时时钟
说明： 实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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i2s_input
基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)
- 2020-12-14 16:49:14下载
- 积分：1
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鲍伍利乘数
鲍伍利乘数用于 2 四位二进制数比普通的那种使用更少的触发器。
- 2022-06-14 09:18:49下载
- 积分：1
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PrinciplesofVerifiableRTLDesignpart2
非常好的verilog书
国际牛人写的
适合各个阶段学习的人(Very good Verilog books were written in the international cattle suitable for the various stages of learning)
- 2007-09-28 11:26:38下载
- 积分：1
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DTMB
能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分：1
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apb_uart
这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
- 2021-04-12 14:18:57下载
- 积分：1
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时序分析
XILINX 时序约束使用指南笔记 ——时序约束介绍 时序约束方法 时序约束原则等(XILINX time series constraints use guide notes -- time series constraints introducing time series constraint principles, etc.)
- 2017-12-21 11:37:56下载
- 积分：1
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vga_interface_requiring_core_regeneration
vga interface with text rom. font size 80x40. core need core regeneration.
- 2013-05-19 02:09:10下载
- 积分：1
