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串口通信（发送和接收）
基于verilog语言的串口通信，可以实现数据的发送和接收，代码清晰明了
- 2022-01-21 20:44:37下载
- 积分：1
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PWM
飞思卡尔智能车芯片模块程序 MC9S12XS128 测试通过(freescale smart car for MC9S12XS128)
- 2011-08-04 10:34:33下载
- 积分：1
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FPGA
基于FPGA的数字系统设计,包含原理、工程应用和案例。(FPGA-based digital system design, including theory, engineering applications and cases.)
- 2010-10-12 21:34:00下载
- 积分：1
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VHDL_example_100
本书通过100个实例，详细介绍便件描述语言vHDL的各种语法现象及其在专用集成电路(AHc)设计蝴还中的使用方法。(the book through one hundred examples, it detailed description language vHDL pieces of the phenomenon and its various grammatical in ASIC (AHc) were also designed butterfly The usage.)
- 2007-03-25 09:57:05下载
- 积分：1
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SimpleVOut-master
说明： SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
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CACPU
basic cpu design in verilog
- 2016-01-11 23:26:01下载
- 积分：1
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chuankou
说明： 本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
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ModelSim_
FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)
- 2013-07-24 19:20:57下载
- 积分：1
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s
说明： 反应力测试 利用图片的变换根据用户点击的反应时间判断(Reaction force measurement using the picture of the transformation reaction time based on user clicks judgment)
- 2013-06-02 20:59:41下载
- 积分：1
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BBTHG_II_t_x
KDP晶体二倍频与三倍频；基于耦合波方程组；已于实验结果校核 (Sum Frequency in KDP)
- 2021-03-16 11:39:21下载
- 积分：1
