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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
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Chebyshev-filter
利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance.
)
- 2013-09-05 20:04:36下载
- 积分：1
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Traffic-lights-at-the-crossroads
一种十字路口交通灯在matlab环境中的实现源码(Traffic lights at the crossroads)
- 2013-05-16 10:18:38下载
- 积分：1
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Multi_function
01 线性调频信号的卷积功能测试（匹配）
02 LFM一维距离像
03 MATLAB联合FPGA仿真输入/输出功能测试
04 解速度模糊
05 扩展目标检测(01 LFM Test function of "conv"
02 LFM Range
03 MATLAB and FPGA
04 resovle speed resolution
05 Extended moving target)
- 2013-05-03 15:53:43下载
- 积分：1
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last
verilog，FPGA的TDC电路设计(verilog ，TDC base on FPGA)
- 2021-01-04 18:48:54下载
- 积分：1
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UART
说明： 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。(The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.)
- 2008-10-09 15:59:20下载
- 积分：1
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FPGA-Design
自己搜集的一些FPGA指南教程，包括一些高工们的经验之谈、设计原则，目前正在学习，有一定帮助，分享给大家(Gather their own of some FPGA guide tutorial, including some senior engineers are the voice of experience, design principles, are learning to have some help, to share to everyone)
- 2012-11-06 10:58:54下载
- 积分：1
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detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system desi...
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
- 2022-04-24 22:44:35下载
- 积分：1
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VGA_Test
说明： 基于FPGA的VGA驱动代码VHDL
在显示屏显示一个汉字(FPGA-based VHDL code of the VGA driver that a character in the display)
- 2009-08-10 14:55:27下载
- 积分：1
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hdlc
HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)
- 2014-08-28 21:37:31下载
- 积分：1
