登录
首页 » VHDL » 32位元浮点数加法器,用于以VHDL编写的32位元CPU

32位元浮点数加法器,用于以VHDL编写的32位元CPU

于 2022-10-08 发布 文件大小:2.24 kB
0 121
下载积分: 2 下载次数: 1

代码说明:

32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • DisplayPort Link training optimization
    说明:  介绍了Displayport规格中lind training的背景研究,设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.)
    2021-01-11 16:48:49下载
    积分:1
  • PS2_Core
    or1200 PS2_Core code
    2010-07-18 23:26:44下载
    积分:1
  • ASKMod
    ASK调制信号的verilog VHL设计,在ise中实现了ASK信号的调制解调。(ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.)
    2017-04-17 10:46:19下载
    积分:1
  • SPI_test
    用FPGA于32进行SPI单向通信,FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)
    2020-06-18 10:40:02下载
    积分:1
  • dlx.tar
    these is about code for dlx processor
    2010-03-15 17:52:53下载
    积分:1
  • RSA密码芯片的FPGA实现[1].part1.rar RSA密码芯片的FPGA实现[1].part1.rar...
    RSA密码芯片的FPGA实现[1].part1.rar RSA密码芯片的FPGA实现[1].part1.rar-RSA password chip FPGA realization of [1]. Part1.rarRSA password chip FPGA realization of [1]. Part1.rar
    2022-08-13 06:54:28下载
    积分:1
  • 明德扬科教之Gvim_20170511
    FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)
    2021-04-14 19:58:55下载
    积分:1
  • 一个16位cpu的vhdl代码。具体内容我也不清楚,自己慢慢研究吧...
    一个16位cpu的vhdl代码。具体内容我也不清楚,自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
    2022-01-26 05:10:10下载
    积分:1
  • ug_dsp_builder
    本文是Altera公司编写的dspbuilder的设计方法,但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)
    2008-12-14 01:33:58下载
    积分:1
  • zhentongbu
    FPGA在通信上的运用:基于VHDL的帧同步程序(Application of FPGA in communication: Based on VHDL frame synchronization procedures )
    2012-11-28 09:10:05下载
    积分:1
  • 696518资源总数
  • 105549会员总数
  • 12今日下载