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QPSK_System
实现QPSK系统的调制解调仿真,基带成形滤波器采用升余弦滚降滤波器,将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)
- 2020-12-22 15:39:07下载
- 积分:1
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LATTICE_ASYNFIFO
LATTICE FPGA FIFO 程序例程,工程详细,全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)
- 2013-09-09 11:10:01下载
- 积分:1
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中值滤波verilog
中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog
- 2023-03-28 00:30:04下载
- 积分:1
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交通灯 verilog HDL 源代码
这是Verilog HDL的一个路灯的源代码。在电路板上的LED代表的绿色,黄色和红色light.After一些固定的时间内,
LED将是命令打开或关闭。此外,时间会倒数,它会被董事会在屏幕上显示。它是为Verilog硬件描述语言的一个
新的学习者非常有用的。
- 2023-06-03 12:10:03下载
- 积分:1
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具备GMII接口和ARP协议功能的千兆以太网控制器
具备GMII接口和ARP协议功能的千兆以太网控制器,经过Xilinx SPATAN-III FPGA验证
- 2023-05-22 19:50:03下载
- 积分:1
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FPGA驱动LCD1602代码
这个是我自己写的LCD1602的代码,经过测试可以再LCD1602上正常运行,由于自己的板子是4线制的,所以通过4线制来通信,对于知道8线数据位编程的同学,不妨试试4线数据位怎么编写
- 2022-03-02 16:10:30下载
- 积分:1
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uart_fifo
一份带有FIFO缓存的UART源码,采用verilog编写,实现批量数据的传输,数据缓存量可以通过修改源码中的FIFO的深度来改变。(This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.)
- 2021-04-25 22:38:46下载
- 积分:1
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encode_64_66
自编的64B/66B编码程序,下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)
- 2011-08-27 10:38:53下载
- 积分:1
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fjq1
介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳
定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)
- 2020-12-01 10:39:28下载
- 积分:1
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turbo_encoder
在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)
- 2021-04-19 09:38:51下载
- 积分:1