-
The_entire_FPGA_design_flow_Modelsim_Synplify
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)
- 2009-04-06 10:12:48下载
- 积分：1
-
VHDL程序讲解FIFO与RAM和ROM的数据交换
本资源详细的设计了一个FIFO的用法，将数据从ROM中读取送到FIFO缓存中然后RAM从FIFO缓存中读取数据存到内存中，改程序可以很好的学习三者之间的关系
- 2022-03-19 07:51:46下载
- 积分：1
-
VHDL language H.264 realize the opencore, meaning that documents, information su...
VHDL语言实现H.264的opencore，内涵说明文档、源码和文献等资料。 -VHDL language H.264 realize the opencore, meaning that documents, information such as source code and documentation.
- 2022-01-24 18:33:09下载
- 积分：1
-
verilog-montgomery-RSA
基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)
- 2021-04-27 20:28:44下载
- 积分：1
-
6_ImageBasic
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像基本操作,几何变换,直方图,灰度化处理等(System Generator based image processing engineering, multimedia processing FPGA implementation source code, the basic operation of the image, geometric transformations, histogram, gray processing)
- 2020-10-20 20:07:24下载
- 积分：1
-
全数字fsk调制解调的实现 verilog源码
全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code
- 2023-04-11 15:55:04下载
- 积分：1
-
raised-cosine-filter
代码实现了一个根升余弦成型滤波器，2PAM信号通过此成型滤波器，并且匹配接收，画出了发送和接收波形，验证了代码的正确性。(The code designs a root raised cosine filter,2PAM signal transmitted through the filter and matched using the same filter, I plot the transmitted signal and received signal to verify the correctness of the code.)
- 2012-11-09 21:59:53下载
- 积分：1
-
Cadence_manual_1.2.pdf
Cadence_manual_1.2.pdf
- 2022-01-26 00:20:48下载
- 积分：1
-
PCI9052
用verilog语言编译的pci协议实现，而且有具体的电路图(Compiled with the verilog language pci protocol implementation, but also the specific circuit)
- 2010-01-06 19:17:39下载
- 积分：1
-
16位二进制转化为BCD码
此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)
- 2018-10-31 13:31:13下载
- 积分：1
