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reverse-string
programe reverse a string in c
- 2015-04-13 17:09:26下载
- 积分：1
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PRBS
代码是伪随机数生成和检测的模块，用于通信行业的FPGA编程。包括VHDL和Verilog两种语言的版本。用于做接口测试。(This module generates or check a PRBS pattern.)
- 2021-05-08 11:58:35下载
- 积分：1
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业界标准的Verilog语法格式
verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分：1
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AD_TO_FIFO
A/D采集的数据缓存进入fifo，并通过读信号将FIFO中的数据送入网口(A/D sample data buffer to fifo,and then read enable to ethernet.)
- 2020-07-10 21:08:54下载
- 积分：1
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I2C_ise9migration
说明： IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)
- 2010-04-02 09:26:54下载
- 积分：1
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02_基于ZYNQ的SOC入门基础
说明： VIVADO pl端文档 基于zynq 7020(vivado soc pl example text of zynq)
- 2020-06-17 11:40:02下载
- 积分：1
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bayer_3RGB_interpolation
一个基于FPGA用verilogHDL设计的bayer格式转RGB格式的模块，本人设计(a code used for bayer_3RGB_interpolation ,which based on FPGA by verilogHDL)
- 2011-12-25 21:58:05下载
- 积分：1
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prueba
Test for VHDL just a student version
- 2016-11-17 18:49:33下载
- 积分：1
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RapidIO_avalonst
RapidIO：使用Avalon-ST直通接口的实现方法，可以在fpga上实现(rapidio altera)
- 2017-05-31 22:50:11下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
