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1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES...
1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-04-30 11:01:06下载
- 积分：1
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VGA_Controller
用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)
- 2013-07-24 08:58:24下载
- 积分：1
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simpleCpu
relative cpu design implementation
- 2013-08-14 21:22:39下载
- 积分：1
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4-code
设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)
- 2016-05-24 17:00:31下载
- 积分：1
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Encoder_SSI_Veryilog
说明： 本文详细描述了SSI协议的通讯格式、原理及应用电路,并采用verilog语言实现了SSI通讯协议.设计实用电路并实现了与绝对值编码器的通讯(SSI protocol described in detail the communication format, principle and application circuit, and use verilog language of the SSI protocol. Practical circuit design and implementation of the communication with the absolute encoder)
- 2020-12-28 20:59:02下载
- 积分：1
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serial_adder
串行加法器的vhdl描述，用两个移位寄存器和一个全加器，一个d触发器实现(The VHDL description of the serial adder, with two shift registers and a full adder, a D trigger)
- 2020-11-10 21:19:46下载
- 积分：1
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CODE_VHDL_INITIALIZING 在 2 线液晶显示，你可以打开/关闭液晶屏 (KHỞI TẠO HIỂN THỊ 2 HÀNG 液晶电视 VÀ CÓ THỂ TẮT/MỞ 液晶屏)
- 2022-05-25 12:11:46下载
- 积分：1
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设计与验证Verilog_实例，经典的HDl书籍，强烈推荐
设计与验证Verilog_实例，经典的HDl书籍，强烈推荐-Design and verification Verilog_ examples Hdl classic books, strongly recommend
- 2022-04-23 19:09:22下载
- 积分：1
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svpwm3
说明： 基於空間向量調變的開關法，在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)
- 2019-01-04 16:07:37下载
- 积分：1
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sopc_test
在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)
- 2014-04-30 10:24:55下载
- 积分：1
