-
dpll
说明： 在quartus下搭建的数字锁相环，能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)
- 2020-06-21 01:00:02下载
- 积分：1
-
LATTICE_ASYNFIFO
LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)
- 2013-09-09 11:10:01下载
- 积分：1
-
4-to-1
4选1数据选择器，有使能端控制，4个数据输入，2个地址端，1个输出(4 1 data selector, enable end control, four data inputs, two addresses end, an output)
- 2012-10-15 18:48:38下载
- 积分：1
-
zidong-shouhuoji
用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)
- 2014-01-05 20:42:49下载
- 积分：1
-
sram
说明： FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)
- 2019-08-19 16:03:39下载
- 积分：1
-
ADC
AD转换的Matlab程序，将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率)，然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)
- 2012-12-18 11:01:40下载
- 积分：1
-
ddr2_controller
DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)
- 2010-02-23 09:16:50下载
- 积分：1
-
f500
verilog coding for butterworth filter with cut off
frequency with 500hz
- 2014-02-19 15:37:09下载
- 积分：1
-
布斯算法结构的 VHDL 代码
布斯算法用于在计算机体系结构的两个二进制现在的乘法。随着处理器为转移的运行情况良好，不能轻易做乘法这就是为什么正在使用它。
- 2022-08-08 00:31:29下载
- 积分：1
-
jiaotongdeng
数字电路课程设计，用VHDL实现交通灯的控制(Digital circuit design using VHDL control of traffic lights)
- 2014-06-16 18:26:53下载
- 积分：1
