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                        submodule
                        
                          verilog 双模块算术平均值计算模块,子模块在时钟上升沿技术,高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)                         
                            - 2011-01-05 22:49:16下载
- 积分:1
 
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                        Microcomputer-Principle
                        
                          该书介绍了英特尔的80x86CPU和一些串行通信芯片,以及汇编语言。(The book introduces the Intel 80x86CPU and some serial communications chip, and assembly language.)                         
                            - 2013-07-27 14:55:25下载
- 积分:1
 
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                        Walsh
                        
                          沃尔什函数序列sequency的verilog编程实现,含有测试文件(the Walsh sequence in sequency order)                         
                            - 2020-07-03 08:20:01下载
- 积分:1
 
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                        CORDIC16
                        
                          16次迭代的CORDIC算法,精度很高,可应用于计算反正切值(16 iterations of the CORDIC algorithm, high accuracy, can be applied to calculate arctangent)                         
                            - 2010-06-01 15:23:27下载
- 积分:1
 
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                        aurora_IP
                        
                          Aurora协议是一款高带宽、低成本、可扩展、框架简洁、适合点对点串行数据传输的协议。(Aurora protocol is a high-bandwidth, low-cost, scalable, simple framework for point to point serial data transfer protocol.)                         
                            - 2017-03-10 17:16:22下载
- 积分:1
 
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                        PCI-based--DSG
                        
                          基于PCI的数字信号发生器
关键词:PCI总线,PCI9054,FPGA,卡尔曼滤波器(PCI-based digital signal generator
Keywords: PCI bus, PCI9054, FPGA, Kalman filter)                         
                            - 2016-06-12 20:41:45下载
- 积分:1
 
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                        FPGA 乒乓球
                        
                          此代码基于cyclone III开发。通过一排LED充当乒乓球,模拟打乒乓的游戏                         
                            - 2022-01-28 08:38:44下载
- 积分:1
 
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                        SERDES_handbook
                        
                          SERDES资料,包括reliability_handbook,serdes_handbook,serdes_introduction(SERDES doc,include reliability_handbook,serdes_handbook,serdes_introduction)                         
                            - 2017-01-12 18:28:41下载
- 积分:1
 
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                        Block-cipher-lock
                        
                          密码锁verilog源代码,包括四个七段数码管显示模块,设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)                         
                            - 2014-01-11 23:57:19下载
- 积分:1
 
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                        Synthesis_and_Fpga_Implementation_of_UAR
                        
                          Synthesis and fpga implementation of UART                         
                            - 2018-12-03 14:06:02下载
- 积分:1