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HB1
说明: 半带滤波器,用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)
- 2020-12-23 10:29:06下载
- 积分:1
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2D4N_com
2维4节点的UEL单元,嵌入UMAT,采用j2 mises屈服准则(2d4nodes uel elements, with umat codes, and j2 mises flow rule)
- 2014-06-04 20:43:21下载
- 积分:1
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SystemVerilog验证++测试平台编写指南
说明: 基于sv的uvm平台搭建实战,对于验证方法学来说,分层的测试平台是一个关键的概念。虽然分层似乎会使测试平台变得更复杂,但它能够把代码分而治之,有助于减轻工作负担,而且重复利用效率提升。验证平台可以类似分为五个层次:信号层、命令层、功能层、场景层和测试层。(Construction of UVM platform based on SV)
- 2020-07-19 16:18:46下载
- 积分:1
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一个用FPGA语言设计数字秒表的程序,有相关的源程序和说明
一个用FPGA语言设计数字秒表的程序,有相关的源程序和说明-FPGA design using a digital stopwatch language of the procedures and instructions related to the source
- 2022-02-02 02:15:47下载
- 积分:1
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一款介绍Soc使用的PDF文档供大家看和实践,还是有一定参考价值的!...
一款介绍Soc使用的PDF文档供大家看和实践,还是有一定参考价值的!-A description Soc using PDF documents for everyone to see and practice, there are still some reference value!
- 2022-01-25 23:50:29下载
- 积分:1
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chuankou_huihuan
FPGA与PC端实现串口数据的收发,先从PC端接收数据,然后发回给电脑,可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)
- 2020-06-16 10:20:01下载
- 积分:1
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degilent atlys board ucf
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- 2022-04-10 00:32:44下载
- 积分:1
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VHDL 编写的RAM例子
VHDL 编写的RAM例子-RAM prepared VHDL example
- 2023-03-23 05:20:03下载
- 积分:1
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FPGA
基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
- 2023-01-20 11:30:04下载
- 积分:1
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Hardware Description Language VHDL of the frequency counter program can be used...
硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.
- 2023-01-23 07:20:04下载
- 积分:1