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供大家学习以太网VHDL和Verilog代码
以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
- 2022-08-21 10:09:17下载
- 积分：1
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Cerradura
Conduct a digital system ( electronic lock ) using
hierarchic methodology .
An electronic lock is a device that allows access or
opening of a system , as long as the key or combination to enter match
with which it is predefined in said lock .
- 2014-10-10 15:41:14下载
- 积分：1
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FPGA的发展
FPGA开发全攻略，工程师创新宝典，由张国斌等书写-FPGA development
- 2022-02-21 00:39:00下载
- 积分：1
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基于SOPC EP2C5开发板的I2C总线的A/D D/A例程
基于SOPC EP2C5开发板的I2C总线的A/D D/A例程-A/D AND D/A routings interfaced with i2c based on sopc ep2c5
- 2022-01-25 22:27:04下载
- 积分：1
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在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件...
在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware description HDL files and driver files
- 2022-03-19 04:54:11下载
- 积分：1
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VHDL Digital Full ADDER Logic Program
- 2022-08-03 08:35:11下载
- 积分：1
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led
基于fpga的led点阵控制系统软件程序设计(Led dot matrix control system based on fpga software program design)
- 2013-01-14 11:50:35下载
- 积分：1
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8.8-URAT-VHDL
URAT VHDL程序与仿真 URAT the VHDL program and Simulation
(URAT the VHDL program and Simulation
)
- 2012-04-09 20:53:45下载
- 积分：1
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at7_ex04
通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)
- 2018-04-09 18:41:52下载
- 积分：1
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SoC sample Code using Altera Xcaliber, good usefull SoC.
SoC sample Code using Altera Xcaliber, good usefull SoC.
- 2022-02-04 17:46:18下载
- 积分：1
