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VC707_MIG_DDR3
说明: VC707_MIG_DDR3.sim文件夹中是仿真的文件:testbench和DDR3模型参数
VC707_MIG_DDR3.srcs文件夹中是源文件,包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters
VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)
- 2020-10-16 19:20:53下载
- 积分:1
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FPGA读写SDRAM的VHDL程序(已经测试过)
FPGA读写SDRAM的VHDL程序(已经测试过)-SDRAM read and write the VHDL program FPGA (already tested)
- 2022-05-20 21:52:20下载
- 积分:1
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可实现找钱功能的自动售邮票机,可买两种邮票,一元的和五角的...
可实现找钱功能的自动售邮票机,可买两种邮票,一元的和五角的-Money function can be realized stamp vending machine, to buy two stamps, one dollar and the Pentagon
- 2022-07-09 12:07:56下载
- 积分:1
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svtb_ahb_sram
说明: 一款verilog设计的SRAM控制器,可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)
- 2020-06-30 13:40:02下载
- 积分:1
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占空比1:1的通用分频模块
占空比1:1的通用分频模块-1:1 generic-frequency module
- 2022-11-11 08:45:03下载
- 积分:1
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vga_demo2
VGA controller : Genarate a VGA signal from your inout information as color info of each pixel
- 2010-06-24 09:26:57下载
- 积分:1
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MIT_Press_Circuit_Design_with_VHDL_(2004)
circuit design with VHDL e-book MIT Press....
- 2009-05-08 00:33:54下载
- 积分:1
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Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
- 2022-07-06 17:29:44下载
- 积分:1
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DAC1220
高精度直流信号源,DAC1220,20位分辨率,双极性输出(High-precision DC source, DAC1220,20 bit resolution, bipolar output)
- 2021-02-28 16:29:35下载
- 积分:1
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fpga1394
这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.(This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.)
- 2005-03-31 16:09:51下载
- 积分:1