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5
fpga paper function fff(fpga paper function)
- 2010-03-11 23:15:24下载
- 积分：1
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XDS100v3-Design-Kit-1.0-Setup
压缩包是ti xds100v3 Design kit的安装文件，安装后有原理图、PCB文件，与DSP接口采用FPGA，安装后有源码，是VHDL格式的，支持开源，降低开发成本(Compression package is ti xds100v3 Design kit installation file after installation schematics, PCB files, and DSP interface with FPGA, after installation source is VHDL formats, support for open source, reduce development costs)
- 2014-08-28 09:36:34下载
- 积分：1
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5_ADC_Lab
基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)
- 2015-11-18 10:56:16下载
- 积分：1
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modelsim_ug
Mentor Graphics ModelSim User s Guide Software v6.3g
- 2010-04-18 13:30:25下载
- 积分：1
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5_ADC_Lab
altear max10 adc demo，实验使用了2个adc，最大支持18路adc(altear max 10 demo with 2 adc， max support 18 channel adc)
- 2021-04-21 14:48:49下载
- 积分：1
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Verilog语言手册
Verilog Language Manual
- 2022-04-19 20:28:43下载
- 积分：1
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DAC5578_I2C
说明： TI公司的DAC5578驱动程序，经测试过的，CSDN资源分享(DAC5578 Driver of TI Company Tested and CSDN Resource Sharing)
- 2020-06-18 21:40:01下载
- 积分：1
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mux21a
在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分，顺序语句的执行方式十分类似于普通软件语言的程序执行方式，都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)
- 2008-12-24 18:25:20下载
- 积分：1
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用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS
用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
- 2022-03-24 12:46:20下载
- 积分：1
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exercise
使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)
- 2014-02-20 16:20:33下载
- 积分：1
