登录
首页 » VHDL » 使用Veriolog hdl 编写手机屏测试程序.

使用Veriolog hdl 编写手机屏测试程序.

于 2023-04-25 发布 文件大小:2.03 kB
0 100
下载积分: 2 下载次数: 2

代码说明:

使用Veriolog hdl 编写手机屏测试程序.-Veriolog hdl prepared to use cell phone screen test.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • vhdl
    New files for pudn website
    2018-06-30 07:30:02下载
    积分:1
  • cpu
    用全加器设计8位运算器逻辑电路图 2、根据逻辑电路用 VHDL编程实现 3、调试编译通过后,仿真 (this file can help you learn the design of cpu)
    2010-01-05 09:56:11下载
    积分:1
  • hammingaTB
    Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.
    2013-11-06 15:45:02下载
    积分:1
  • USERMANUL
    LPC4357开发板采用ARM的Cortex-M4微控制器LPC4357。内置一个ARM Cortex-M0协处理,CPU运行频率高达204MHz,片内集成1MB Flash和36KB SRAM。开发板采用独立核心板设计,核心板集成64MB SDRAM、128MB NAND-Flash、4MB SPI-Flash。核心板上的摄像头接口可直接连接各种型号的摄像头,两侧160P排针接口引出了除EMC总线外的LPC4357芯片所有功能管脚。 开发板提供丰富的外设接口,包括以太网、液晶屏、摄像头、USB-Host、USB-OTG、SD卡、RS232、RS485、CAN、耳机、麦克风、温度传感器、AD/DA、JTAG仿真器等。此外,开发板提供一个14P扩展接口,包括1路UART、1路SPI、1路I2C、4个IO、3.3V、5V,可以很方便的扩展自己的外围电路。(DS-LPC4357 development board using the Cortex-M4 microcontroller LPC4357 ARM s. A built-in ARM Cortex-M0 co-processor, CPU operating frequency up to 204MHz, 1MB Flash and 136KB SRAM integrated on chip. Development board using an independent core board design, the core board integrates 64MB SDRAM, 128MB NAND-Flash, 4MB SPI-Flash. Camera core board interface can be directly connected to various types of cameras, both sides 160P pin interface leads to the outside of the bus in addition to EMC LPC4357 chip all the functions of the pins. Development board provides a rich set of peripheral interfaces, including Ethernet, LCD screen, camera, USB-Host, USB-OTG, SD card, RS232, RS485, CAN, headphone, microphone, temperature sensor, AD/DA, JTAG emulator, etc. . In addition, the development board provides a 14P expansion interfaces, including one-way UART, 1 road SPI, 1 channel I2C, 4 个 IO, 3.3V, 5V, can easily expand their peripheral circuits.)
    2016-02-23 16:58:53下载
    积分:1
  • tdc
    线性伸展TDC的verilog,包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)
    2021-01-04 18:58:55下载
    积分:1
  • VHDL的寄存器读写参考,可自己根据要求重新修改,本示范只做参考用...
    VHDL的寄存器读写参考,可自己根据要求重新修改,本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only
    2022-09-23 06:45:03下载
    积分:1
  • 本程序实现不同频率时钟的产生及其相互转化
    本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation
    2022-03-06 09:31:43下载
    积分:1
  • jiaozhijiejiaozhi
    VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)
    2020-07-17 15:08:49下载
    积分:1
  • fenpin
    开发工具是quartus II 7.0以上版本,这是一个verilog语言的分频器设计,个人作业设计,供参考学习(verilog,quartus II 7.0)
    2012-06-15 11:02:00下载
    积分:1
  • FSK
    频移键控FSK的Verilog实现,带测试文件,并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)
    2020-09-03 11:28:07下载
    积分:1
  • 696518资源总数
  • 106161会员总数
  • 5今日下载