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thesis
thesis for simple virus detection processor which is developed in xilinx
- 2015-02-18 23:51:11下载
- 积分:1
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vey2v585
说明: 该代码实现了俄罗斯方块旋转,左右移动,快速下降,计分和VGA显示等基本功能(This code realizes the basic functions of Russian square rotation, left-right movement, rapid decline, scoring and VGA display.)
- 2020-06-17 19:00:01下载
- 积分:1
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source
说明: altera fpga 实现fft,用fft IP核,有matlab仿真代码(Altera FPGA implementation of FFT, FFT IP core, matlab simulation code)
- 2020-12-18 20:29:11下载
- 积分:1
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counter
设计一个十进制计数器模块,输入端口包括 reset、up_enable 和 clk,输出端口为 count
和 bcd,当 reset 有效时(低电平),bcd 和 count 输出清零,当 up_enable 有效时(高电
平),计数模块开始计数(clk 脉冲数),bcd 为计数输出,当计数为 9 时,count 输出一
个脉冲(一个 clk周期的高电平,时间上与“bcd=9”时对齐)(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))
- 2013-04-13 19:53:29下载
- 积分:1
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基于verilog的串口收发协议
基于verilog的串口收发程序,使用组合逻辑加时序逻辑的方式编写,易于灵活修改!
- 2022-09-06 08:45:02下载
- 积分:1
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ml555_block_plus_example_es
说明: 高速FPGA 开发设计资料,包括全部的设计方案和开发例程,可快速入手FPGA设计。(High speed FPGA development and design data, including all the design schemes and development routines, can quickly start FPGA design.)
- 2020-08-03 11:44:12下载
- 积分:1
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22WALSH
1、掌握WALSH码产生的原理和WALSH码的特性。
2、掌握WALSH码的产生和特性分析的软件仿真。
3、掌握WALSH码的硬件产生方法。
(1, master code WALSH WALSH code generation principles and characteristics. 2, master WALSH code generation and characterization of the software simulation. 3, master code WALSH hardware generation approach.)
- 2020-07-03 08:40:01下载
- 积分:1
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velocity_Verilog
速度表(velocity)要求:1.显示汽车Km/h数;2.车轮每转一圈,有一传感脉冲;每个脉冲代表1m的距离;3.采样周期设为10s;
4.要求显示到小数点后边两位;5.用数码管显示;6. 最高时速小于300Km/h。(约为83.3m/s)
(use verilog to realize velocity)
- 2020-07-13 15:08:51下载
- 积分:1
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RTC
verilog编写的RTC(实时时钟)包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)
- 2009-12-19 23:51:50下载
- 积分:1
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v5_emac
以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)
- 2013-12-15 23:08:11下载
- 积分:1