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16ChannelDeserializer
LVDS De-serialization
- 2019-06-20 14:53:25下载
- 积分：1
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LEDWATER
说明： LIUSHUIDENG VHDLYUYAN XIADE SHUIDENG(LEDWATER I WRITER IT MYSILF.IT'S EASY ! YOU CAN WRITER IT,TOO)
- 2017-08-31 11:17:13下载
- 积分：1
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DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M...
DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
- 2023-07-27 16:00:03下载
- 积分：1
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USB口的设计，包括驱动程序的设计，以及软件的安装演示，软件的介绍，以及工作模式...
USB口的设计，包括驱动程序的设计，以及软件的安装演示，软件的介绍，以及工作模式-USB port design, including the driver design, and installation of software, presentation, software presentation, and working models
- 2023-02-04 17:15:08下载
- 积分：1
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m_xulie
这是用verilogHDL写的m序列发生器，简单易用，代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)
- 2015-05-27 20:21:26下载
- 积分：1
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等精度频率计
基于FPGA的等精度频率计，包括工程，doc和一些查找资料(An equal precision frequency meter based on FPGA, including engineering, Doc, and some lookup data)
- 2020-10-30 21:39:57下载
- 积分：1
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UART to send the complete procedure, including the complete source code of nucle...
UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.
- 2022-01-28 15:16:09下载
- 积分：1
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随机数发生器
随机数发生器
- 2023-04-30 09:25:03下载
- 积分：1
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counter (2)
This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.
- 2017-07-18 19:24:12下载
- 积分：1
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4ASKmod2
讲述4ASK的原理并附有matlab调制解调的源码。。。。。。。。。。
注：原来上传的4ASKmod.zip不要下(The principle tells 4ASK together with modulation and demodulation matlab source. . . . . . . . . . Note: The original upload 4ASKmod.zip not down)
- 2013-07-10 00:01:10下载
- 积分：1
