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src
假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分：1
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Send-Program
program send sms by sim900 module
- 2012-08-08 18:25:11下载
- 积分：1
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verilog编写的一个fir滤波器，
本代码实现一个fir滤波器，结合matlab对数据进行进行验证，最后用modesim对编写的代码进行仿真，最终用matlab和fpga实现一个功能正常的fir低通滤波器，这里附有源代码，并且用verilog代码编写，具有很大的参考作用对于刚学习fpga的朋友，希望你们能真正的对所学的东西感兴趣，这个是我上传代码的初衷，希望你们学业进步，继续做一个对技术有信心的人才。
- 2022-08-14 19:24:41下载
- 积分：1
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GUI
1）选择一个语音信号作为分析对象，或录制一段语音信号； 2）对语音信号进行采样，画出采样前后语音信号的时域波形和频谱图； 3）利用MATLAB中的随机函数产生噪声加入到语音信号中，使语音信号被污染，然后进行频谱分析； 4）设计用于处理该语音信号的数字滤波器，给出滤波器的性能指标，画出滤波器的频率响应； 5）对被噪声污染的语音信号进行滤波，画出滤波前后信号的时域波形和频谱，并对滤波前后的信号进行比较和分析； 6）回放各步骤的语音信号，给出相应处理程序及运行结果分析。(1) Select a voice signal as an analysis object, or record a voice signal 2) sampling the voice signal, draw the waveform and frequency spectrum of the time domain before and after sampling the speech signal 3) using the random function in MATLAB generated noise was added to the speech signal, the speech signal to be contaminated, and then spectrum analysis 4) for processing the speech signal, the digital filter design, given the performance of the filter to draw the filter' s frequency response 5) on the noise pollution of the speech signal is filtered, time-domain waveform and spectrum draw before and after filtering the signal before and after filtering, and the signal for comparison and analysis 6) playback of the speech signal for each step, given the results of the corresponding processing procedures and run analysis.)
- 2021-03-18 17:29:19下载
- 积分：1
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EnDat
ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)
- 2021-05-12 22:30:02下载
- 积分：1
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PS2_Core
or1200 PS2_Core code
- 2010-07-18 23:26:44下载
- 积分：1
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SRAM6bit
sram 6bit仿真模型，verilog编写(sram 6bit simulation model, verilog prepared)
- 2021-03-16 13:59:22下载
- 积分：1
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DDS_Power
FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)
- 2007-04-17 23:43:32下载
- 积分：1
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完整SD控制器！支持文件系统。
32-bit Wishbone Interface
• DMA
• Buffer Descriptor
• Compliant with SD Host Controller Spec version 2.0
• Support SD 4-bit mode
• Interrupt-on-completion of Data and Command transmission
• Write/Read FIFO with variable size
• Internal implementation of CRC16 for data lines and CRC7 for command line
Wishbine 总线使用。完整的SD卡控制器，支持文件系统，高速传输。
- 2023-05-06 18:00:02下载
- 积分：1
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COMPLETE-OFDM
完整的OFDM仿真程序，包括QPSK,16QAM调制，基于MATLAB，各个步骤都有详细的说明。(OFDM simulation program, based on the complete MATLAB, every step is described in detail.)
- 2013-05-23 11:31:57下载
- 积分：1
