mydesign

代码说明：

  基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具， 各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。 (FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simulation tools, the module using Verilog HDL to design and package, the top-level use of graphic design, and finally the simulation results obtained using the Matlab description points to draw waveforms.)

文件列表：

mydesign
........\add1.v
........\add2.v
........\addr_ctrl.bsf
........\addr_ctrl.v
........\addr_ctrl.v.bak
........\addr_ctrl.vwf
........\clock.asm.rpt
........\clock.bsf
........\clock.done
........\clock.fit.rpt
........\clock.fit.smsg
........\clock.fit.summary
........\clock.flow.rpt
........\clock.map.rpt
........\clock.map.smsg
........\clock.map.summary
........\clock.pin
........\clock.qpf
........\clock.qsf
........\clock.qws
........\clock.sim.rpt
........\clock.tan.rpt
........\clock.tan.summary
........\clock.v
........\clock.v.bak
........\clock.vwf
........\convolute.bsf
........\convolute.v
........\convolute.v.bak
........\convolute.vwf
........\db
........\..\add_sub_0sh.tdf
........\..\add_sub_1sh.tdf
........\..\add_sub_fah.tdf
........\..\add_sub_fnh.tdf
........\..\add_sub_gah.tdf
........\..\add_sub_ndh.tdf
........\..\add_sub_nqh.tdf
........\..\add_sub_odh.tdf
........\..\add_sub_ooh.tdf
........\..\add_sub_poh.tdf
........\..\altsyncram_d591.tdf
........\..\altsyncram_vc91.tdf
........\..\clock.asm.qmsg
........\..\clock.cbx.xml
........\..\clock.cmp.cdb
........\..\clock.cmp.hdb
........\..\clock.cmp.logdb
........\..\clock.cmp.rdb
........\..\clock.cmp.tdb
........\..\clock.cmp0.ddb
........\..\clock.cmp2.ddb
........\..\clock.dbp
........\..\clock.db_info
........\..\clock.eco.cdb
........\..\clock.eds_overflow
........\..\clock.fit.qmsg
........\..\clock.hier_info
........\..\clock.hif
........\..\clock.map.cdb
........\..\clock.map.hdb
........\..\clock.map.logdb
........\..\clock.map.qmsg
........\..\clock.pre_map.cdb
........\..\clock.pre_map.hdb
........\..\clock.psp
........\..\clock.pss
........\..\clock.rpp.qmsg
........\..\clock.rtlv.hdb
........\..\clock.rtlv_sg.cdb
........\..\clock.rtlv_sg_swap.cdb
........\..\clock.sgate.rvd
........\..\clock.sgate_sm.rvd
........\..\clock.sgdiff.cdb
........\..\clock.sgdiff.hdb
........\..\clock.sim.cvwf
........\..\clock.sim.hdb
........\..\clock.sim.qmsg
........\..\clock.sim.rdb
........\..\clock.sld_design_entry.sci
........\..\clock.sld_design_entry_dsc.sci
........\..\clock.syn_hier_info
........\..\clock.tan.qmsg
........\..\clock.tis_db_list.ddb
........\..\mult_dns.tdf
........\..\prev_cmp_clock.asm.qmsg
........\..\prev_cmp_clock.fit.qmsg
........\..\prev_cmp_clock.map.qmsg
........\..\prev_cmp_clock.qmsg
........\..\prev_cmp_clock.sim.qmsg
........\..\prev_cmp_clock.tan.qmsg
........\..\wed.wsf
........\dsss.bsf
........\dsss.v
........\dsss.v.bak
........\dsss.vwf
........\fir.bsf
........\fir.v
........\insert.bsf