LIP2242CORE_otp_rom

代码说明：

  Verilog OTP ROM source code

文件列表：

oc8051_defines.v,19313,2007-06-12
oc8051_rom
..........\automake.log,1890,2007-06-30
..........\oc8051_rom.cmd_log,207,2007-06-30
..........\oc8051_rom.dhp,1191,2007-06-30
..........\oc8051_rom.ise,4472,2007-06-30
..........\oc8051_rom.ise_ISE_Backup,4472,2007-06-30
..........\oc8051_rom.lso,6,2007-06-30
..........\oc8051_rom.prj,29,2007-06-30
..........\oc8051_rom.syr,4998,2007-06-30
..........\oc8051_rom.v,123661,2007-06-30
..........\oc8051_rom_summary.html,2641,2007-06-30
..........\oc8051_rom_vhdl.prj,0,2007-06-30
..........\Project.dhp,1090,2007-06-30
..........\xst
..........\...\dump.xst
..........\...\........\oc8051_rom.prj
..........\...\........\..............\ngx
..........\...\........\..............\...\notopt
..........\...\........\..............\...\opt
..........\...\work
..........\...\....\hdllib.ref,66,2007-06-30
..........\...\....\vlg0D
..........\...\....\.....\oc8051__rom.bin,3316,2007-06-30
..........\_xmsgs
..........\__ISE_repository_oc8051_rom.ise_.lock,249,2007-06-30
..........\__projnav
..........\.........\ednTOngd_tcl.rsp,54,2007-06-30
..........\.........\oc8051_rom.gfl,642,2007-06-30
..........\.........\oc8051_rom.xst,1107,2007-06-30
..........\.........\oc8051_rom_flowplus.gfl,314,2007-06-30
..........\.........\parentCreateTimingConstraintsApp_tcl.rsp,11,2007-06-30
..........\.........\runXst_tcl.rsp,38,2007-06-30
..........\.........\sumrpt_tcl.rsp,18,2007-06-30
..........\__projnav.log,2829,2007-06-30
oc8051_rom.v,123661,2007-06-30
otp_defines.v,15311,2007-06-30
otp_rom.v,111495,2007-06-30
otp_rom.v.bak,111413,2007-06-30
transcript,609,2007-06-30
work
....\oc8051_rom
....\..........\verilog.psm,7388,2007-06-30
....\..........\_primary.dat,641,2007-06-30
....\..........\_primary.vhd,351,2007-06-30
....\otp_rom
....\.......\verilog.psm,106595,2007-06-30
....\.......\_primary.dat,18584,2007-06-30
....\.......\_primary.vhd,465,2007-06-30
....\rom0
....\....\verilog.psm,6233,2007-06-30
....\....\_primary.dat,977,2007-06-30
....\....\_primary.vhd,208,2007-06-30
....\rom1
....\....\verilog.psm,6233,2007-06-30
....\....\_primary.dat,977,2007-06-30
....\....\_primary.vhd,208,2007-06-30
....\rom10
....\.....\verilog.psm,6233,2007-06-30
....\.....\_primary.dat,978,2007-06-30
....\.....\_primary.vhd,210,2007-06-30
....\rom100
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom101
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom102
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom103
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom104
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom105
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom106
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom107
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom108
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30
....\......\_primary.vhd,212,2007-06-30
....\rom109
....\......\verilog.psm,6233,2007-06-30
....\......\_primary.dat,979,2007-06-30