PhaseLockedLoop

代码说明：

  This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL). The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.