fpga(CAN)

代码说明：

  fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。(fpga CAN Bus Controller source, each with explanatory documents on the use of methods.)

文件列表：

Chapter9 Sample
...............\canbus
...............\......\.untf
...............\......\automake.log
...............\......\canbus.dhp
...............\......\canbus.npl
...............\......\can_acf.v
...............\......\can_bsp.v
...............\......\can_btl.v
...............\......\can_crc.v
...............\......\can_defines.v
...............\......\can_fifo.cmd_log
...............\......\can_fifo.lso
...............\......\can_fifo.ngc
...............\......\can_fifo.ngr
...............\......\can_fifo.prj
...............\......\can_fifo.stx
...............\......\can_fifo.syr
...............\......\can_fifo.v
...............\......\can_fifo_vhdl.prj
...............\......\can_ibo.v
...............\......\can_register.v
...............\......\can_registers.lso
...............\......\can_registers.prj
...............\......\can_registers.stx
...............\......\can_registers.v
...............\......\can_registers_vhdl.prj
...............\......\can_register_asyn.v
...............\......\can_register_asyn_syn.cmd_log
...............\......\can_register_asyn_syn.lso
...............\......\can_register_asyn_syn.ngc
...............\......\can_register_asyn_syn.ngr
...............\......\can_register_asyn_syn.prj
...............\......\can_register_asyn_syn.stx
...............\......\can_register_asyn_syn.syr
...............\......\can_register_asyn_syn.v
...............\......\can_register_asyn_syn_vhdl.prj
...............\......\can_register_syn.v
...............\......\can_testbench.fdo
...............\......\can_testbench.ndo
...............\......\can_testbench.udo
...............\......\can_testbench.v
...............\......\can_testbench_defines.v
...............\......\can_top.bld
...............\......\can_top.cmd_log
...............\......\can_top.ldo
...............\......\can_top.lso
...............\......\can_top.ngc
...............\......\can_top.ngd
...............\......\can_top.ngr
...............\......\can_top.prj
...............\......\can_top.stx
...............\......\can_top.syr
...............\......\can_top.v
...............\......\can_top.vhdsim_xlate
...............\......\can_top.xlate_nlf
...............\......\can_top_translate.nlf
...............\......\can_top_translate.vhd
...............\......\can_top_vhdl.prj
...............\......\coregen.log
...............\......\coregen.prj
...............\......\prjname.lso
...............\......\timescale.v
...............\......\htm" target=_blank>transcript
...............\......\work
...............\......\....\can_acf
...............\......\....\.......\verilog.asm
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\can_bsp
...............\......\....\.......\verilog.asm
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\can_btl
...............\......\....\.......\verilog.asm
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\can_crc
...............\......\....\.......\verilog.asm
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\can_fifo
...............\......\....\........\verilog.asm
...............\......\....\........\_primary.dat
...............\......\....\........\_primary.vhd
...............\......\....\can_ibo
...............\......\....\.......\verilog.asm
...............\......\....\.......\_primary.dat
...............\......\....\.......\_primary.vhd
...............\......\....\can_register
...............\......\....\............\verilog.asm
...............\......\....\............\_primary.dat
...............\......\....\............\_primary.vhd
...............\......\....\can_registers
...............\......\....\.............\verilog.asm
...............\......\....\.............\_primary.dat
...............\......\....\.............\_primary.vhd
...............\......\....\can_register_asyn
...............\......\....\.................\verilog.asm
...............\......\....\.................\_primary.dat