clkgen
代码说明:
用MATLAB产生各种时钟信号,对于不同的模块产生适当的始终信号.()
文件列表:
clkgen
......\clkgen.cr.mti
......\clkgen.mpf
......\clk_div.v
......\clk_gen.v
......\test.v
......\top.fsdb
......\htm" target=_blank>transcript
......\work
......\....\clk_div
......\....\.......\verilog.asm
......\....\.......\_primary.dat
......\....\.......\_primary.vhd
......\....\clk_gen
......\....\.......\verilog.asm
......\....\.......\_primary.dat
......\....\.......\_primary.vhd
......\....\top
......\....\...\verilog.asm
......\....\...\_primary.dat
......\....\...\_primary.vhd
......\....\htm" target=_blank>_info
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