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PCIe DMA部分文件及重要模块代码（不是工程、含注释）
分析官方xapp1052工程，将发送引擎和接收引擎中的代码进行了详细注释，上传不是工程，只是详细注释的v文件，或将有助于分析修改官方工程。
- 2020-12-02下载
- 积分：1
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verilog_IEEE官方标准手册-2005_IEEE_P1364
The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group
- 2020-12-11下载
- 积分：1
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MATLAB带通滤波器程序
应用切比雪夫滤波器，设计了带通滤波器function y=bandp(x,f1,f3,fsl,fsh,rp,rs,Fs)%带通滤波%使用注意事项：通带或阻带的截止频率与采样率的选取范围是不能超过采样率的一半%即，f1,f3,fs1,fsh,的值小于 Fs/2%x:需要带通滤波的序列% f 1：通带左边界% f 3：通带右边界% fs1：衰减截止左边界% fsh：衰变截止右边界%rp：边带区衰减DB数设置%rs：截止区衰减DB数设置%FS：序列x的采样频率% f1=300;f3=500;%通带截止频率上下限% fsl=200;fsh=600;%阻带截止频率上下限%
- 2020-12-09下载
- 积分：1
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基于51单片机的全自动洗衣机设计（带Protues仿真）
基于51单片机的全自动洗衣机设计（带Protues仿真）。对于51单片机的课程设计和学习51单片机，学习Protues是个好资料。
- 2021-05-06下载
- 积分：1
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KB4474419+KB4490628(X64)+补丁包下载地址.zip
【实例简介】在重装window7较早版本的时候，会因为必要补丁包的缺少导致一些问题。我遇到的问题是在KB4474419+KB4490628(X64)两个补丁包缺少的情况下，安装独显的驱动会提示无法继续安装，该文件压缩包包含两个补丁包和补丁包下载地址，补丁包解压即可用，经过测试两个补丁包没有问题。
- 2021-11-01 00:33:59下载
- 积分：1
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基于MATLAB的数字滤波器设计毕业论文设计
基于MATLAB的IIR数字滤波器的设计 （毕业论文），是一篇设计基于MATLAB的IIR数字滤波器的设计方法和毕业论文，有大量的有用信息。是一篇非常值得下载的毕业论文。
- 2020-12-09下载
- 积分：1
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Gabor二维滤波器——最全
最全的Gabor二维滤波器，包括详细的matlab代码和注释以及分析，对学习Gabor滤波器绝对会有很大帮助。是本人一点一点收集，部分代码是原创，大多都亲自运行测试过。
- 2020-12-05下载
- 积分：1
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北斗三号B1C weil码生成Matlab程序
北斗3号B1C信号测距码生成中，无论是数据分量还是导频分量都用到weil码，本程序仿真B1C数据分量主码的weil码，通过输出头24码片和后24码片与B1C接口文档中的表5-2比较是一致的。
- 2020-12-12下载
- 积分：1
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单相全桥逆变器simulink仿真
单相全桥逆变器simulink仿真，内含SPWM输出模块，可以通过设置调制比/基波频率/载波频率查看逆变器的响应效果。
- 2020-12-05下载
- 积分：1
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TeeChart Pro 2015.15.150420 D4-XE8 full source 源码
该源码理论上支持未来很长一段时间内的任意delphi版本，需要做的可能只是修改一下DEF定义文件宏。以下是我试验并安装成功的过程。我未安装FMX相应组件，安装方法应该与VCL的一样。需要的自行试验。下边只说VCL安装方法：以XE7为例说明，1.将source目录下相应的dpk文件复制到VCL目录，在VCL目录查找*D21*.dpk,找到所有的DPK文件，全部打开，打开过程中会有一些报错提示，不用管它。编译之后再打开就不会再有了。全部打开后，build all即可。2.TeeTree,TeeMaker两个目录也是一样，找到全部的D21.dpk文件，打开，编译。至此，bpl文件包已安
- 2021-05-07下载
- 积分：1
