MIKE21教程
不错的MIKE21中文教程，主要介绍MIKE21水动力模块方面的内容Www.Zlvo.Com42.7风场( Wind forcing)···;;;·36注意:42.8冰盖( ce coverage)4.2.9引潮势( Tidal potential)42.10降水-蒸发( Precipitation- Evaporation)….4142.1波浪辐射应力( Wave radiation)424212源( Sources4342.13水工结构物( Structures)454.2.14初始条件( nitial conditions)42.15边界条件( Boundary conditions)6142.16温度/盐度模块(Tcmpcraturc/Salinity Module)6742.17湍流模块( Turbulence module)42.8解耜( Decoupling)….…6742.9输出( Outputs)…特别说明:本手册部分内容来源于网络。Www.Zlvo.Com第一章模型介绍11简介MIKE21是一个专业的工程软件包,用于模拟河流、湖泊、河口、海湾、海岸及海洋的水流、波浪、泥沙及环境。MIKE21为工程应用、海岸管理及规划提供了完备、有效的设计环境。高级图形川户界面与高效的计算引擎的结合使得MIKE2I在世界范围内成为了一个水流模拟专业技术人员不可缺少的工具。丹麦水力研究所开发的平面二维数学模型MIKE21,曾经在丹麦、埃及、澳洲、泰国及中国香港、台湾等国家和地区得到成功应用,在丬面二维白由表面流数值模拟方面具有强大的功能。目前该软件在中国的应用发展很快,并在一些大型工程中广泛应用,如:长江口综合治理工程、杭州湾数值模拟、南水北调工程、重庆市城市排污评价、太湖富营养模型、香港新机场工程建设等。12MIKE21软件特点(1)用户界面友好,属于集成的 Windows图形界面;(2)具有强大的前、后攵理功能。在前处理方面,能根据地形瓷料进行计算网格的划分;在后处理方面具有强大的分析功能,如流场动态演示及动画制作、计算断面流量、实测与计算过程的验证、不同方案的比较等;(3)多种计算网格、模块及许可选择确俫用户根据自身需求来选择模型(4)可以进行热启动,当用户因各种原因需暂时中断MIKE21模型时,只要在上次计算时设置了热启动文件,再次开始计算时将热启动文件调入便可继续计算,极大地方便了计算时间有限制的用户;(5)能进行干、湿节点和干、湿单元的设置,能较方便地进行滩地水流的模拟:(6)具有功能强大的卡片设置功能,可以进行多种控制性结构的设置,如桥墩、堰、闸、涵洞等(7)可广泛地应用于二维水力学现象的研究,潮汐、水流,风暴潮,传热、盐流,水质,波浪紊动,湖震,防浪堤布置,船运,泥沙侵蚀、输移和沉积等,Www.Zlvo.Com被推荐为河流、湖泊、河∏和海岸水流的二维仿真模拟工具。1.3水动力模块原理131控制方程模型是基于三向不可压缩和 Reynolds值均布的 Navier-SLokes方程,并服从于 Boussinesq假定和静水压力的假定。二维非恒定浅水方程组为Ch Chu chvhSChu ahauvan h6x+=1-a=欧h-a(1-22pa ax po po ph)+-(h12)+hu,Schv chuy chvfuh-ghan h apay po aygh ap2 Po ay Po po po、ax11)+hS式中:t为时间:x,y为笛卡尔坐标系坐标;n为水位;d为静止水深;h=n+d为总水深;tn,v分别为x,y方向上的速度分量;f是哥氏力系数,f=2 osin p,(为地球白转角速度,为当地纬度;g为重力加速度;p为水的密度;Sx、SS分别为辐射应力分量;S为源项;(uy,ν)为源项水流流速。字母上带横杠的是平均值。例如,矿、ν为沿水深平均的流速,由以下公式定义hu= udz, hvdzWww.Zlvo.Com为水平粘滞应力项,包括粘性力、紊流应力和水平对流,这些量是根据沿水深平均的速度梯度用涡流粘性方程得出的:T=2A2A13,2数值解法)空间离散计算区域的空间离散是用有限体积法( Finite volume method),将该连续统体细分为不重叠的单元,单元可以是任意形状的多边形,但在这里只考虑三角形和四边形单元。在MKE软件2007版本只能是三角形网格。浅水方程组的通用形式一般可以写成上(U)=S(U)(1-6)式中:U为守恒型物理向量:F为通量向量;S为源项在笛卡尔坐标系中,二维浅水方程组可以写为OU O(F-F)O(FY-Fy)S(1-7)式中:上标/和分别为无粘性的和粘性的通量。各项分别如下:0hCu+g(FhuyOu Cha0Fk=lhAolhugh42Www.Zlvo.Comadh2thPu cy Pogn+fuhpe gn opythiPo oy Po对方程(46)第i个单元积分,并运用 Gauss原理重写可得出「a(Fa)-JA(1-9)式中:A1为单元g2的面积;I;为单元的边界;ds为沿着边界的积分变量这里使用单太求积法来计算面积的积分,该求积点位于单元的质点,同时使用中点求积法水计算边界积分,方程(49)可以写为∑FnAT=S(1-10)式中:U和S分别为第个单元的U和S的平均值,并位于单元中心;NS是单元的边界数;^厂,为第j个单元的长度阶解法和二阶解法都可以用于空间离散求解。对于二维的情况,近似的Riemann解法可以用来计算单元界面的对流流动。使用Roc方法时,界面左边的和右边的相关变量需要估计取值。二阶方法中,空间准確度可以通过使用线性梯度重构的技术来获得。而平均梯度可以用由 jawahar和 Kamath于2000年提出的方法来估计,为了避免数值振荡,模型使用了二阶TVD格式。(2)时间积分考虑方程的一般形式aU=G(U)1-11)对于二维模拟,浅水方程的求解有两种方法:一种是低阶方法,另一种是高阶方法。低价方法即低阶显式的Euer方法Un1=Un+△G(Un)(1-12)式中:为时间步长。高阶的方法为以如下形式的使用了二阶的 Runge kuttaWww.Zlvo.Com方法n12=Un+△G(U,)Un+1=Un+△G(Un+12)(1-13)(3)边界条件1)闭合边界沿着闭合边界(陆地边界),所有垂直于边界流动的变量必须为0。对于动量方程,可以得知沿着陆地边界是完全平稳的。2)开边界开边界条件可以指定为流量过程或者是水位过程3)千湿边界处理动边界问题(T湿边界)的方法是基于赵棣华(1994)和 Sleigh(1998)的处理方式。当深度较小时,该问题可以被重新表述,通过将动量通量设置为零以及只考恳质量通量来实现。只有当深度足够小时,计算不考虑该网格屮元。每个单元的水深会被监测,并且单元会被定义为干、半干湿和湿。单元面也会被监测,以确定淹没边界。满足下面两个条件单元边界被定义为淹没边界:首先单元的一边水深必须小于hn,且另一边水深必须大于h;第二,水深小于hn的单元的静水深加上另一单元表面高程水位必须大于零。满足下亩两个条件单元会被定义为干单元:首先单元中的水深必须小于干水深hn;另外,该单元的三个边界中没有一个是淹没边界。被定义为干的单元在计算中会被忽略不计。单儿破定义为半干:如果单元水深介于h和hm之间,或是当水深小于hy但有一个边界是淹没边界。此时动量通量被设定为0,只有质量通量会被计算。单元会被定义为湿:如果单元水深大于ha。此时动量通量和质量通量都会在计算中被考虑。如果模型中的区域是处在τ湿边交替区,为了避免模型计算岀现不稳定性,使用者可以启用 Flood and Dry选项。在这个情形下使用者必须设定一个干水深Www.Zlvo.Com( drying depth),淹没深度( flooding water depth)和湿水深( wetting depth)者必须满足hn
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MicroElectronic Circuit Design
微电子电路设计第五版,Richard C. Jaeger, Traveis N. Blalock编著。FIETH EDITIONMICROELECTRONICHM-M- CIRCUIT DESIGNRICHARD C. JAEGERAuburn UniversityTRAVIS N. BLALOCKUniversity of VirginiaMcGrawEducationGrawEducationMICROELECTRONIC CIRCUIT DESIGN. FIFTH EDITIOPublished by McGraw-Hill Education, 2 Penn Plaza, New York, NY 10121 CopyrightC 2016 by McGraw-Hill EducationAll rights reserved. Printed in the United States of America. Previous editions 2011, 2008, and 2004. No part of thispublication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system,without the prior written consent of McGraw-Hill Education, including, but not limited to, in any network or otherelectronic storage or transmission, or broadcast for distance learninSome ancillaries, including electronic and print components, may not be available to customers outside the United StatesThis book is printed on acid-free pape1234567890DOw/DOw1098765ISBN978-0-07-352960-8MHID0-07-352960-5sident Products markets Kurt LVice President, General Manager, Products Markets: Marty Langece President, Content Design Delivery: Kimberly Meriwether DavidManaging director: Thomas TimpGlobal Publisher Raghu srinivasanDirector. Prodrelopment: RoDirector, Digital Content Development: Thomas Scaife, Ph DProduct develoVincent brashMarketing manager: Nick Mc faddenDirector, Content Design Delivery: Linda avenariusProgram meSchillingContent Project Managers: Jane Mohr, Tammy Juran, and Sandra M. SchneeBuyer: Jennifer PickelDesign: Studio Montage, St Louis, MOContent Licensing Specialist: DeAnna DausenerCompositor: MPS LimitedPrinter.R. DonnellAll credits appearing on page or at the end of the book are considered to be an extension of the copyright pageLibrary of Congress Cataloging-in-Publication DataJaeger. Richard cMicroelectronic circuit design/Richard C. Jaeger, Auburn University,Travis N. Blalock, University of Virginia. --Fifth editionpages cmIncludes bibliographical references and indexISBN978-0-07-352960-8(alk. paper)-ISBN0-07-338045-8(alk. paper)d 1. Integrated circuits--Design and construction. 2. Semiconductors--Design and construction. 3. Electronic circuitesign. I. Blalock, Travis N. Il. TitleTK7874.J3332015621.3815-dc232014040020The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does not indicatean endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not guarantee the accuracy ofthe information presented at these siteswww.mhhe.comTOTo Joan, my loving wife and life long partnerRichard C. JaegerIn memory of my father, Professor Theron vaughnBlalock, an inspiration to me and to the countlessstudents whom he mentored both in electronicdesign and in life.Travis n blalockBRIEF CONTENTSPreface xxChapter-by-Chapter Summary XXV12 Operational Amplifier Applications 685PART ONE13 Small-Signal Modeling and LinearSOLID-STATE ELECTRONICS AND DEVICESAmplification 77014 Single-Transistor Amplifiers 8411 Introduction to Electronics 32 Solid-State Electronics 4115 Differential Amplifiers and Operational Amplifier3 Solid-state Diodes and Diode circuits 72Design 9524 Field-Effect Transistors 14416 Analog Integrated Circuit Design Techniques 10315 Bipolar Junction Transistors 21517 Amplifier Frequency Response 111318 Transistor Feedback Amplifiers andPART TWOOscillators 1217DIGITAL ELECTRONICSAPPENDICES6 Introduction to Digital Electronics 2837 Complementary MOS (CMOS) Logic Design 359A Standard Discrete Component Values 12918 MOS Memory Circuits 414B Solid-State Device Models and sPIce simulationParameters 12949 Bipolar Logic Circuits 455C TWo-Port Review 1299PART THREIndex 1303ANALOG ELECTRONICS10 Analog Systems and Ideal OperationalAmplifiers 51711 Nonideal Operational Amplifiers and FeedbackAmplifier Stability 587CONTENTSPreface xxCHAPTER 2Chapter-by-Chapter Summary XXVSOLID-STATE ELECTRONICS 41PART ONE2.1 Solid-State Electronic materials 432.2 Covalent bond model 44SOLID-STATE ELECTRONICS2.3 Drift Currents and mobility inAND DEVICES 1Semiconductors 472.3.1 Drift Currents 47CHAPTER 12.3.2 Mobility 48INTRODUCTION TO ELECTRONICS 32.3.3 Velocity Saturation 482.4 Resistivity of Intrinsic Silicon 491.1 A Brief History of Electronics: From2.5 Impurities in Semiconductors 50Vacuum Tubes to Giga-Scale Integration 52.5.1 Donor Impurities in silicon 511.2 Classification of Electronic Signals 82.5.2 Acceptor Impurities in Silicon 511.2.1 Digital signals 92.6 Electron and hole concentrations in1.2.2 Analog Signals 9Doped semiconductors 511.2.3 A/D and D/A Converters--Bridging2.6.1Type Material (ND >NA)52the analog and Digital2.6.2 p-Type Material (N,A>ND)53Domains 102.7 Mobility and Resistivity in Doped1.3 Notational conventions 12Semiconductors 541.4 Problem-Solving Approach 132.8 Diffusion currents 581.5 Important Concepts from Circuit2. 9 Total Current 59Theory 152.10 Energy Band Model 601.5.1 Voltage and current Division 152.10.1 Electron-Hole pair generation in1.5.2 Thevenin and norton circuitan intrinsic semiconductor 60Representations 162.10.2 Energy Band Model for a Doped1.6 Frequency Spectrum of ElectronicSemiconductor 61Signals 212.10.3 Compensated semiconductors 611.7 Amplifiers 222.11 Overview of Integrated circuit1.7.1 Ideal operational amplifiers 23Fabrication 631.7.2 Amplifier Frequency Response 25Summary 661.8 Element Variations in Circuit Design 26Key Terms 671.8.1 Mathematical modeling ofReference 68Tolerances 26Additional Reading 681.8.2 Worst-Case Analysis 27Problems 688.3 Monte Carlo analysis 291.8.4 Temperature Coefficients 32CHAPTER 31.9 Numeric Precision 34SOLID-STATE DIODES AND DIODE CIRCUITS 72Summary 34Key Terms 353.1 The pn Junction Diode 73References 363.1.1 pn Junction Electrostatics 73Additional Reading 363.1.2 nternal diode currents 77Problems 363.2 The i-v Characteristics of the diode 78VIllContents3.3 The Diode Equation: A Mathematica3.15 Full-Wave Bridge Rectification 123Model for the diode 803.16 Rectifier Comparison and Design3.4 Diode Characteristics under reverse, ZeroTradeoffs 124and forward bias 833.17 Dynamic Switching Behavior of the Diode 1283.4.1 Reverse bias 833.18 Photo diodes, solar cells, and3. 4.2 Zero bias 83Light-Emitting Diodes 1293.4.3 Forward Bias 843.18.1 Photo diodes and3.5 Diode Temperature Coefficient 86Photodetectors 1293.6 Diodes under reverse bias 863.18.2 Power Generation from Solar Cells 1303.6.1 Saturation Current in real3.18. 3 Light-Emitting Diodes(LEDs)13Diodes 87Summary 1323.6.2 Reverse Breakdown 89Key Terms 1333.6.3 Diode model for the breakdownReference 134Region 90Additional Reading 1343.7 pn Junction Capacitance 90Problems 1343.7.1 Reverse bias 903.7.2 Forward Bias 91CHAPTER 43.8 Schottky Barrier Diode 933.9 Diode SPICE Model and layout 93FIELD-EFFECT TRANSISTORS 1443.9.1 Diode Layout 944.1 Characteristics of the MOS Capacitor 1453.10 Diode Circuit Analysis 954.1.1 Accumulation Region 1463.10.1 Load-Line Analysis 964.1.2 Depletion Region 1473.10.2 Analysis Using the Mathematical4.1.3 Inversion Region 147Model for the diode 974.2 The nmos transistor 1473.10.3 The Ideal diode model 1014.2.1 Qualitative i-v Behavior of the3.10.4 Constant Voltage Drop Model 103NMOS Transistor 1483.10.5 Model Comparison and4.2.2 Triode Region Characteristics ofDiscussion 104the nmos transistor 1493.11 Multiple-Diode Circuits 1054.2.3 On Resistance 1523.12 Analysis of Diodes Operating in the4.2.4 Transconductance 153Breakdown Region 1084.2.5 Saturation of the i-v3.12.1 Load-Line Analysis 108Characteristics 1543.12.2 Analysis with the Piecewise4.2.6 Mathematical model in theLinear model 108Saturation (Pinch-off)3.12.3 Voltage regulation 109Region 1553.12.4 Analysis Including Zener4.2.7 Transconductance in saturation 156Resistance 1104.2.8 Channel-Length Modulation 1563.12.5 Line and Load Regulation 1114.2.9 Transfer characteristics and3.13 Half-Wave Rectifier Circuits 112Depletion-Mode MosFETs 1573.13.1 Half-Wave Rectifier with resistor4.2.10 Body Effect or SubstrateLoad 112Sensitivity 1593.13.2 Rectifier Filter Capacitor 1134.3 PMOS Transistors 1603.13.3 Half-Wave Rectifier with rc load 1144.4 MOSFET Circuit Symbols 1623. 13.4 Ripple Voltage and Conduction4.5 Capacitances in MOS Transistors 165Interval 1154.5.1 NMOs Transistor Capacitances in3.13.5 Diode Current 117the Triode region 1653.13.6 Surge Current 1194.5.2 Capacitances in the Saturation3.13.7 Peak-Inverse-Voltage(PlV)Rating 119Region 1663.13.8 Diode Power Dissipation 1194.5.3 Capacitances in Cutoff 1663.13.9 Half-Wave Rectifier with Negative4.6 MOSFET Modeling in SPICE 167Output Voltage 1204.7 MOS Transistor Scaling 1683.14 Full-Wave Rectifier Circuits 1224.7.1 Drain Current 1693. 14.1 Full-Wave Rectifier with Negative4.7.2 Gate Capacitance 169Output Voltage 1234.7.3 Circuit and power densities 169ContentsIX4.7.4 Power-Delay Product 1705.3 The pnp Transistor 2234.7.5 Cutoff Frequency 1705.4 Equivalent Circuit Representations for the4.7.6 High Field Limitations 171Transport Models 2254.7.7 The unified mos transistor model5.5 The i-v Characteristics of the bipolarIncluding High Field Limitations 172Transistor 2264.7.8 Subthreshold conduction 1735.5.1 Output Characteristics 2264.8 MOs Transistor Fabrication and layout5.5.2 Transfer characteristics 227Design Rules 1745.6 The Operating Regions of the Bipolar4.8.1 Minimum Feature size andTransistor 227Alignment Tolerance 1745.7 Transport Model Simplifications 2284.8.2 Mos Transistor Layout 1745.7.1 Simplified Model for the Cutoff4.9 Biasing the NMOS Field-EffectRegion 229Transistor 1785.7.2 Model Simplifications for the4.9.1 Why Do We Need Bias? 178Forward-Active Region 2314.9.2 Four-Resistor Biasing 1805.7.3 Diodes in Bipolar Integrated4.9.3 Constant Gate-Source VoltageCircuits 237Bias 1845.7.4 Simplified Model for the4.9.4 Graphical analysis for theReverse-Active Region 238Q-Point 1845.7.5 Modeling Operation in the4.9.5 Analysis Including Body Effect 184Saturation Region 2404.9.6 Analysis Using the Unified5.8 Nonideal Behavior of the bipolarModel 187Transistor 2434.10 Biasing the PMos Field-Effect Transistor 1885.8.1 Junction Breakdown Voltages 2444.11 The junction Field-Effect Transistor5.8.2 Minority-Carrier Transport in theUFET190Base Region 2444.11.1 The JFET With Bias Applied 195.8.3 Base Transit time 2454.11.2 JFET Channel with Drain-Source5.8.4 Diffusion Capacitance 247Bias 1935.8.5 Frequency Dependence of the4.11.3 n-Channel jfet i-v Characteristics 193Common-Emitter current gain 2484.11.4 The p-Channel JFET 1955.8.6 The Early Effect and Early4.11.5 Circuit Symbols and JFET ModelVoltage 248Summary 1955.8.7 Modeling the Early Effect 2494.11.6 JFET Capacitances 1965.8.8 Origin of the Early Effect 2494.12 JFET Modeling in Spice 1965.9 Transconductance 2504.13 Biasing the JFET and Depletion-Mode5.10 Bipolar Technology and sPiCe Model 251MOSFET 1975.10.1 Qualitative Description 251Summary 2005.10.2 SPICE Model Equations 252Key Terms 2025.10.3 High-Performance BipolarReferences 202Transistors 253Problems 2035.11 Practical bias circuits for the bjt 2545.11.1 Four-Resistor bias network 256CHAPTER 55.11.2 Design Objectives for theBIPOLAR JUNCTION TRANSISTORS 215Four-Resistor bias network 2585.11.3 terative Analysis of the5.1 Physical Structure of the BipolarFour-Resistor bias circuit 262Transistor 2165.12 Tolerances in bias circuits 2625.2 The Transport Model for the npn5. 12.1 Worst-Case Analysis 263Transistor 2175. 12.2 Monte Carlo Analysis 2655.2.1 Forward Characteristics 218Summary 2685.2.2 Reverse Characteristics 220Key Terms 2705.2.3 The Complete Transport ModelReferences 270Equations for Arbitrary BiasProblems 271Conditions 221
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