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linux下组播（双向收发）
1、支持双向收发的组播，仅供参看，若有错误，请指出；2、带一个网卡接口的PC1跑send_recv, 带两个网口的PC跑recv_send程序，PC1发送两个组播数据分别给PC2的两个网卡收，PC2的第一个网卡发送组播数据给PC1收；
- 2020-12-10下载
- 积分：1
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matlab读取rgb图像转为hsi图像并显示出rgb图、灰度图、hsi图
此函数用于将rgb图像转为hsi图像并显示出rgb图、灰度图、hsi图 ，输入：JPG或JPEG或BMP等一般图片名称（加后缀），输出：rgb图、灰度图、hsi图，返回值：hsi矩阵
- 2021-05-06下载
- 积分：1
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纳什均衡求解 博弈论 matlab
【实例简介】压缩包含源代码和原理文献，可以求解n对象博弈的混合策略纳什均衡，原作者是印度Bapi Chatterjee
- 2021-10-30 00:33:11下载
- 积分：1
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《设计模式》清华大学出版社刘伟源码
本书系统介绍了设计模式。全书共分27章，内容包括统一建模语言基础知识、面向对象设计原则、设计模式概述、简单工厂模式、工厂方法模式、抽象工厂模式、建造者模式、原型模式、单例模式、适配器模式、桥接模式、组合模式、装饰模式、外观模式、享元模式、代理模式、职责链模式、命令模式、解释器模式、迭代器模式、中介者模式、备忘录模式、观察者模式、状态模式、策略模式、模板方法模式和访问者模式。[1] 本书结合大量实例来学习GoF设计模式，针对每一个设计模式均提供了一或两个实例，并对每一个模式进行了详尽的讲解，每一章最后均配有一定量的习题。
- 2021-05-06下载
- 积分：1
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OFDM 16QAM matlab_simulink仿真 mdl
OFDM 16QAM matlab_simulink仿真
- 2020-12-08下载
- 积分：1
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MFC实现简单网络聊天程序
MFC实现简单网络聊天程序，利用Visual C++中MFC实现的网络socket程序，简单实现了网络聊天的功能。程序中有服务器程序和客户端程序。很好的学习资源。了SDcksoce类型确定G落户端服务器名称职消C服务器端端口号连接关闭消息发送发送接收soCksket类型确定C客尸端服务器名称「职消眼多器端端口号监听关闭单自发送发送接收新建类回网类的类型: MFC Class确定- class information取消NatMyocetFile nMySocket. cppChange.Base class:CAsyncSocketDialog IDThe base class does not require a dialog resource.AutomatioC Nonf Automationc Createable ty tyne inr MySockiMy SocketThe base class does not support automation.= ER MySack classes中 CAboutDlgpublic:+t ChySockADDf uperation官 CMySockDlgpubliCMuLSockett口 GlobalsGo to definitionAdd Memk点 ad Member variab1e点 ud VE Ludt futchAdd Windows Message Handler套 Referencesd classesBase Classe式 dd to ga11C Hey Folder,ap by Accessy Docking ViewHi deropertCass.JRes0…目Fle.A/AFX INSEHew virtual Override for class IySocketNew virtual FunctionsExisting virtual function overrides确定OnAcceptOnclose取消CoNnectOnOutof BanddataAdd HandlerOnReceiveOnsenAdd and editReceiveSendEdit ExistingOnAcceptu: Called to notify a sacket that it may call AcceptHey Virtual Override for class sOcketNew Virtual FunctionsExisting virtual function overrides确定OnOutoiBandDataAcCeptReceiveOnclose取消enCoNnectOnReceiveAdd HandlerOnSend and editEdit ExistingOnSendl: Called when the socket can send datasocket类型确定C客户端服务器名称Edt取消广服务器端蒲口号Edit连接关闭消息ditAdd夏 ember Function发送Member function name:OKOn ConnectCancel接收Message: BN_CLICKEDObject ID: IDC BCONNECT=l EP My Sock classesif(nError Cc语 CAboutDigCAsonycSockt CMySockApp"L CMySockDlg+. MySocketGo to Definit自 GlobalsGo To Dialog EditorAdd Member functionAdd Member variableAad Virtual FunctionAdd Windows: Message handleRefeBase classesAdd to Gallery画 Folder甲 by Aceessv Docking ViHi de會 Properties((CHySECAsyncsockCass,°Res0,Fie…添加成品函数配区函数类型m:void确定数描述取消OnAcceptiAccess厂 StaticPublicProtectedPrivate厂rual
- 2021-05-06下载
- 积分：1
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matlab 2014b HDL Coder Users Guide
Matlab 官方有关于HDL coder开发的详细技术文档， HDL Coder可以把Simulink模型、MATLAB代码和Stateflow框图生成位真、周期精确、可综合的Verilog和VHDL代码，很适合用于FPGA/ASCI的快速开发，里面还有大量的例程等等ContentsHDL Code generation from MATLaBMATLAB Algorithm DesignData Types and scope1-2Supported data TUsuppyted data type1-3Scope for variables1-3Operators1-4Arithmetic operate1-4Relational operators1-4ogical Operators1-5Control flow statements1-6Vector Function Limitations related to Control1-7PersistentⅤ ariables1-8Persistent Array variables1-10Complex data Type Support1-11Declaring complex signaIs1-11Conversion Between Complex and real signals1-12Support for vectors of Complex Numb1-12ystem Objects1-14Why use System objects?1-14Predefined System Object1-14User-Defined System ob1-14Limitations of HDL Code Generation for SystemObjects1-15System object Examples for HDL Code Generation.. 1-16Predefined System Objects Supported for HDL CodeGeneration1-17Load constants from a mat-file1-18Generate Code for User-Defined System Objects1-19How To Create a User-Defined System object1-1User-Defined System object Example1-19Map Matrices to ROM1-22Fixed-Point bitwise Functions1-231-23Bitwise Functions Supported for HDl Code Generation 1-23Fixed-Point Run-Time Library functions1-29Fixed-Point function limitations1-33Model State with Persistent variables and SysteObjects1-34Bit Shifting and bit rotation1-8Bit Slicing and Bit Concatenation1-41Guidelines for Efficient hdL code1-43MATLAB Design Requirements for HDL CodeGeneration1-44What is a matlab test bench?1-45MATLAB Test Bench Requirements and bestractices1-46MATLAB Test Bench requirements1-46MATLAB Test bench best practices1-46ContentsMATLAB Best Practices and Design Patterns forHDL Code generation2Model a counter for hdl code generation2-2MATLAB Counter2-2MATLAB Code for the counter2-3Best Practices in this Example2-4Model a state machine for HDL Code Generation2-5MATLAB State machinesMATLAB Code for the Mealy State MachineMATLAB Code for the moore state machine2-7Best practic2-9Generate hardware Instances For local functions2-10MATLAB Local functions2-10MATLAB Code for mlhdlc two counters. m2-10Implement RAM USing MATLAB Code2-13Implementation of RAM2-13Implement RAM Using a Persistent Array or Systemobject Properties2-13Implement RAM Using hdl. RAM2-14For-Loop best Practices for HDL Code generation2-16MATLAB Loops2-16Monotonically Increasing Loop Counters2-16Persistent Variables in Loops2-17Persistent Arrays in Loops2-17Fixed-Point Conversion3Floating-Point to Fixed-Point Conversion3-2Fixed-Point Type Conversion and Refinement3-16Working with Generated Fixed-Point Files3-26Specify Type Proposal Options3-33Log Data for Histogram3-37Automated Fixed-Point Conversion3-40License Requirements3-40Automated Fixed-Point Conversion Capabilities3-40Code Coverage3-42Proposing Data Types3-45Locking Proposed Data Types3-47Viewing functions3-47lew1ariables3-48Istogram ...3-54Function Replacements3-56Validating Types3-57g Numerics3-57Detecting Overflows3-57Custom plot functions3-59Visualize Differences Between Floating-Point and Fixed-Point results3-61Inspecting Data Using the Simulation Data Inspector 3-67What Is the Simulation Data Inspecto3-67Import Logged Data3-67Export Logged data3-67Group signals3-67Run options3-68Create Report3-68Comparison Options3-68Enabling Plotting Using the Simulation Data Inspector 3-68Save and Load simulation Data Inspector Sessions3-68Enable Plotting Using the Simulation Data Inspector 3-70From the UI3-70From the Command Line3-70Replacing Functions Using Lookup TableApproximations·3-72Replace a custom function with a lookup Table3-73From the UI3-73i ContentsFrom the Command line3-81Replace the exp Function with a Lookup Table3-84From the ui3-84From the Command line3-92Data Type Issues in Generated Code3-94Enable the highlight Option in a MaTLAB CoderProject3-94Enable the Highlight Option at the Command Line... 3-94Stowaway doubles3-94Stowaway singles3-94Expensive Fixed-Point operations3-94Code GenerationCreate and set Up Your Project4-2Create a New Project4-2Open an Existing ProjectAdd Files to the project4-4Primary Function Input Specification4-6When to Specify Input Properties4-6Why You must Specify Input Properties4-6Properties to Specify4-6Rules for Specifying Properties of Primary Inputs4-8Methods for Defining Properties of Primary Inputs4-8Basic hdl code generation with the workflowAdvisor4-10HDL Code Generation from System Objects4-14Generate Instantiable code for functions4-19How to generate Instantiable Code for Functions4-19Generate Code Inline for Specific Functions4-19Limitations for instantiable code generation forFunctions4-19Integrate Custom HDL Code Into MATLAB Design.. 4-21Define the hdl. Black Box System object4-21Use System object In MATLAB Design Function4-23Generate HDL Code4-23limitations for hdl. black box4-26Enable matLab function block generation4-27Requirements for MaTLAB Function Block Generation 4-27Enable matlab function block generation4-27Results of matlab function block generation4-27System Design with HDL Code Generation fromMATLAB and simulink4-28Generate Xilinx System Generator Black Box Block4-32Requirements for System Generator Black Box BlockGeneration4-32Enable System Generator black Box block GeResults of System Generator Black Box Bloc neration4-32Generation4-33Generate Xilinx System Generator for DsP black boxfrom MATLAB HDL Design4-34Generate HDL Code from MATLAB Code Using theCommand line interface4-40Specify the Clock Enable rate4-45Why specify the clock Enable rate?4-45How to Specify the clock Enable rate4-45Specify Test Bench Clock Enable Toggle rate4-47When to Specify Test Bench Clock Enable Toggle rate4-47How to Specify Test Bench Clock Enable Toggle rate4-47Generate an HDL Coding Standard report fromMATLAB4-49Using the hdl Workflow advisor4-49Using the Command Line4-51Generate an HDL Lint Tool script4-53How To generate an hdl lint Tool Script4-53ContentsGenerate a Board-Independent Ip core from MATLAB 4-55Generate a board-Independent Ip core4-55Requirements and Limitations for IP Core generation4-57Minimize clock enables4-58Using the GUi4-59Using the Command Line4-59Limitations4-59VerificationVerify Code with HDL Test Bench5-2Generate Test bench with file i/oWhen to Use file i/o In Test bench5-5How Test bench generation with file i/o works5-5Test Bench Data files5-5How to generate Test bench with file i/o5-6Limitations When Using File 1/0 In Test Bench5-6DeploymentGenerate Synthesis Scripts6-2Optimization7RAM Mapping7-2Map persistent Arrays and dsp. Delay to RAM7-3How To Enable RaM Mapping7-3RAM Mapping requirements for Persistent Arrays andSystem object PropertiesRAM Mapping Requirements for dsp. Delay Systemob7-6RAM Mapping Comparison for MATLAB Code7-8Pipelining7-9Port registers7-9Input and Output Pipeline registers7-9Variable pipelining7-9Register Inputs and Outputs7-10Insert Input and Output Pipeline registers7-11Distributed Pipelining7-12What is Distributed Pipelin7-12Benefits and Costs of Distributed pipelining7-12Selected Bibliograph7-12Pipeline matlab variables7-13Using the hdl Workflow Advisor7-13Using the Command Line Interface7-13Limitations of MatlAB Variable Pipelining7-13Optimize MatLAb loops7-15oop Streaming7-15Loop unrolling7-15How to Optimize maTLaB loops7-15Limitations for MaTLAB Loop Optimization7-16Constant Multiplier optimization7-17Specify constant multiplier optimization7-19Distributed Pipelining for Clock Speed Optimization7-20Map Matrices to Block RAMs to Reduce Area7-27Resource Sharing of Multipliers to Reduce Area7-32Loop streaming to Reduce Area7-41Contents
- 2020-12-10下载
- 积分：1
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BT656 verilog代码720*576
该源码在FPGA上实现BT656格式的输出，将RGB888装换成BT656 ，bt656为720*576.
- 2020-12-11下载
- 积分：1
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斯坦福机器学习公开课CS229讲义作业及matlab代码资料
个人整理 斯坦福公开课 机器学习CS229课程 较全讲义、作业和matlab代码。
- 2021-05-06下载
- 积分：1
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地质dips汉化版
地质dips 玫瑰花图，是一种用以表示节理空间方位及其发育程度的图解。其作法是:首先对一定地区范围内的节理进行系统测量，将测得的节理产状及密度数据按空间方位间隔分组(如5°或10°为一组)，求出每组的节理数节理玫瑰图节理玫瑰图量和平均走向(或倾向)。然后在标明地理方位的圆内，以半径方向表示节理方位，以半径上的长度单位表示该组节理的数量，将各组节理投入图上，连接相邻各投影点(如某一方位无节理，则连至圆心)，即得到节理玫瑰花图。表示节理走向的图叫走向玫瑰花图，只作上半圆;表示节理倾向的图叫节理倾向玫瑰花图，为全圆形;表示节理倾角的图叫节理倾角玫瑰花图
- 2020-11-28下载
- 积分：1
