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最大团问题
最大团问题代码实现 简单易懂 适合算法学习
- 2020-12-09下载
- 积分：1
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收藏的许多MD2模型
个人收集的许多经典MD2模型 内涵纹理图片学CG编程的可以下载使用
- 2020-12-04下载
- 积分：1
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k60中文数据手册
呕心沥血找到的，k60的很全的数据手册了，20兆~K6OP144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6, Nov 2011第一章关于本文档1.1概述1.1.1目的夲文档描述了飞思卡尔K60系列微控制器的特征、结构和编稈方法1.1.2读者本文档上要是面向即将或者是已经使用K60开发系统的系统设计工程师和软什应用开发者。1.2习惯性约定1.2.1编号制度下的下标标志着不冋的编号系统下标标识b二进制的数字:例如十进制5用二进制表示为101b。某些情况下二走制数字也是用前缀0b来表小进制数字:一般在容易混淆的地方才会便用这个下标。一般情况下,十进制数字不使用下标h六进制数字:例如|进制60用|六进制3Ch来表示。茉些情况下,十六进制也使用前缀0X来表示。1.2.2标识符号本文件使用一下标识符号举例说明placeholder. x斜体的项H是为您提供的占位符的信息。斜体文字也用于出版物的标题和强调。纯小写字母也被用来作为单一的字母和数字的占位符。coae固定宽度的类型表示必须严格按照显示的文本进行输入。它用于指令助记符,指令,标示符,子命令,参数,和运算符。固定宽度的类型乜可用于示例代码。指令助记符和命令在文本和表格中仝部使用大与,例如:BSR。SRISCM]括号中的助记待表示寄存器某个字段的命名,例如SR寄存器的SCM位(段)。REVNOL6: 4, XAD[7: 0]括号内使用冒号隔开的数字表示●寄仔器某个命名字段:例如 REVNO6:4」表示REVNO寄存器的06位。●单个总线的信号范围:例如XAD7:0表示XAD总线的0-7号位。EditbyiliE:soonli@qq.comK6OP144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6, Nov 20111.2.3特殊说明卜列的词汇具有特妹的含义:术含义assert某个信号的状态如下所示置高时会被激活置低时会被激活deasserted某个信号的状态如下所示置高时会被禁止置低时会被禁止reserved个内存的空间,寄存器,或者区域是留作将来使用的,写入时会产生不可预料的结果EditbyiliE:soonli@qq.comK6OP144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6, Nov 2011作者黑li源文件名称:K60P44M0SF2 RM. pdf源文件版本:K60 Sub-Family reference manual,Rev.6,Nov201目标文件版本:0.1最后编辑日期:2012.04.21.17.37修改说明:初稿,夲人水平有限,红色部分是在是没能直接翻译出来。汗,别笑我哈EditbyiliE:soonli@qq.comK6OP144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6, Nov 2011第二章引言2.1概述夲章概述了 Kinetis系列以及其中的K60系列,还对设备所涵盖的模块进行了概括描述。2.2K60系列引言K60微控制器系列具有以下性能:IEEE1588以太网,全速和高速USB2.00n-The-Go带改备充电探测,硬件加密和防窜改探测能力。肀富的模拟、通信、定时和控制外改从100LQFP封装256KB闪存开始可扩展到256 MAPBGA1MB闪存。大闪存的K60系列器件还可提供可选的单精度浮点单元、NAND內存控制器和DRAM控制器2.3功能模块分类器件按照功能分为不同的模块,下面的章节对每个功能模块有着史详细的描述。表格2-1功能模块分类模块描述ARM Rotex-M4内核32位 ARM Crotex-M内核,只有DSP指令和单精度浮点运算单元,1.25DMIPS / MHZ,基于ARMv7结构,在某些系列中还包括16KB的数据/指令高速缓冲。系统模块系统集成控制模块电源管理和模式控制多种电源模式可供选择:运行、等待、停止和掉电模式低漏电流唤陧单元杂项控制单元交义开关内存保护单元内部总线直接内存访问(DM)控制器与复用器,增加可用的DMA请求外部看门狗存储内部存储器包括程序存储器FlexNvMFlexRAM可编程 FLASH编程加速内存SRAM外部存储和设备控制总线接口: FlexBus串行可编程接口: EzPortNAND flash控制器时钟可选的多个时钟源:包括内部时钟和外部时钟为系统提供系统时钟的振蕩器EditbyiliE:soonli@qq.comK6OP144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6, Nov 2011为实时时钟提供时钟源的振荡器加CRC模块硬件加窣和随机数发牛器模拟集成可编程放大增益的高速AD转换器模拟比较器DA转换器内部参老电压定时器可编程延时模块柔性定时器周期性中断定时器低功耗定时器载波调制定时器实时时钟通信以太网MAC控制器支持IEEE1588协议USB0TG内嵌全速/低速PHYUSB支持设备充电检测功能USB自带电压调节功能髙速USB控制器UPI接凵CANSPI12CUARTSD主机控制器人机界面GPIO硬件电容触摸屏接口2.3.1 Rotex-M4內核模块器件内包含以下核心模块表格2-2核心模块模块描述ARM Cortex M4ARM Cortex内核是最新的 Cortex系列处理器主要针对成本敏感、目标确定性、中断驱动的应用而推出的Cortex M内核是基于ARMv7构架,: Thumb-21SA了集兼容 Cortex w3、 Cortex m1和 Cortex mo核心Cortex M4改进包括增加了ARMv7 Thumb2DSP(与ARMv7A/R构架相兼容的),32位SIMD指令(单指令多数据饱和运算指令中断控制器(NVIC)ARM7-M构架的异常和中断处理器(NVIC)使用可重新定位的中断向量表,支持多个可配置优先级的外部中断和个不可屏版中断EditbyiliE:soonli@qq.comK6OP144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6, Nov 2011重映射寄存器简化了编程难度,中断控制单元包含着中断函数的地址,相应的中断程序地址通过指令总线在中断向量表中杏找获得。前十六个入口分配给内核的内部中断,剩下的由外围器件使用。异步唤醒中断控制器(AWIC)在停止模式下,异步唤酲中断控制器檢测异步唤醒事件,并向时钟控制单元发送信号来唤醒系统时钟。当系统时钟启动后,中断控制器开始检测中断,进行常规中断和事件的处理。调试接冂绝大部分器件的调试部分都是基于AM的 CoreSight构架,此构架提供了四个调试接口°IEEE1149.1JTAGIEEE 1149. 7 JTAG (CJTAGrial Wire debug (SWD)ARM Real-time Trace nterface2.3.2系统模块器件内包含以卜系统模块表2-2系统模块模块描述系统集成控制模块(S)系统集成控制模块实现部分模块的·些基本的配置功能系统控制模块(SMC)系统控制模控制和保护系统在各个电源模式的切换,控制电源管毘模块(Pλ),在电源切换时复位整个系统。电源管珥模块(PMO)电源箮理单元提供多种电源模式。不同的电源模式可以为使用者提供最佳的功耗模式。包括上电复位,可编程阀值的掉电检测。低漏唤醒单元L)低漏唤醒单元支持多种内部/外部唤醒模式杂项控制模块(MCM设置嵌入式跟踪调试单元交叉开关(XBS)交叉开关连接着主机总线和外围器件总线,他能实现总线上所有的主机访问任意的从机,在不同的主机访问相同的从机时提供优先级仲裁内存保护单元(MPU提供内存保护和任务隔离功能,并监视总线上主机和从机的通信外围设备总线根据交义开关的配置,位大部分外国器件的存取提供接口。DMA复用器( DMAMUXDMA复用器在众多的DMA请求中,挑选出16个传递给DMA控制器内存直接读取控制器(DMA)外部看门狗监视器EWM软件看门狗(WDOG)EditbyiliE:soonli@qq.comK6OP144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6, Nov 20112.3.3存储和存储接囗器件包含以下的存储器和存储接口表格2-4存储和存储接口模块描述闪存( Flash memory)程序存储区,可执行代码的非易失存储器FlexMemory:包含以下类聖的存储器LexNvm:非易失存储器,可是存放可执行代码,数据或者是模拟 EEPROMFlexray:随机读取寄存器,可以用作传统的RAM,也可用作扃耐写的 EEPROM或者是加速闪存编程编程闪存:编程加速RAM,用于加速 Flash编程。闪存控制器管片上和外围的存储模块的接∏(Flash memory controller)随机动态存储器(SRAM)内部的RAM,一部分RAM在低漏模式下仍能保持供电。随机动态存储器控制器管珥核心和外设存取系统RAM。(SRAM controller)系统寄存器块32位的寄存器,在VDD供电的听有电源模式下都可以访问BAT寄存器块32位的寄存器,在VBAT供电的所有电源模式下都可以访可编程串行接口( EzPort)和业界标准的SPI闪存使用相同的的串行接口,命令集为其子集。能够读、擦除和编程闪存闪存编程后用复位命令重启系统FlexBus六个独立的、可由用户设置的片选信号,可以与外部SRAM、PROM、 EPROM、 EEPROM、闪存和其他外设无缝接∏8位、16位和32位数据总线宽度,提供复用或非复用的地址和数据总线的配置2.3.4时钟器件包含以下的时钟模块表2-5时钟模块模块描述多时钟发生器(MG)提供多个时钟源包括锁相环-压控振荡器锁频环-数控振荡器内部参考时钟可以为其他片上外设提供时钟系统时钟振荡器系统振荡器,在与外部晶体或谐振器的结合EditbyiliE:soonli@qq.comK6OP144M100SF2RM. pdfK60 Sub-Family Reference Manual, Rev. 6, Nov 2011为MCU产一个参考时钟实时时钟振荡器独立电源供电的实时时钟振荡器提供一个32KHZ时钟信号,当然他也可以用作主振荡器为系统提供时钟信号。2.3.5安全和完整性模块器件包含以下的安全和完整新模块表26安全和完整性模块模块描述加密加速单元(CAU)支持DES、3DFS、AES、MD5、SHA-1和SHA-256算法简单的C调用飞思卡尔优化后的加密函数随机数4成器(RNG)支持数字签名标准中定义的密钥牛成算法(参考http://www.itl.nistgov/fipspubs/fip186.htm)集成的熵源能够为RNGB提供熵,以获取种子冗余循环校验(CRC)采用16位或32位移位寄存器的CRC发生器电路16/32位CRC用户可配置可编程的生成器多项式·误码检测功能可以检测所有单、刈、奇误码及大多数多位误码可编程的初始种子值高速CRC计算通过转置寄存器转置输入数据和CRC结果,此为可选特性,用于某些字节是⊥sb格式的应用2.3.6模拟外设器件包含以下的模拟模块表2-7模拟模块模块描述16位具有可编程增益功能的ADC16位的逐次逼近型ADC,具有可编程增益功模拟比较器全电压蒞闱内比较两个模拟输入信号6位的DAC64抽头的梯形电阻网络,向需要电压基准的应用提供基准12位的DAC低电压通用型DAC,可以输出到外部引脚,也作为一个模拟比较或者是ADC的输入。电压参考(VRF可配置的修止寄存器,以0.5m为单位递增,在复位后自动加载室内温度值。可以用于医疗,比如说血糖仪。为模拟外设或者是电压传感器提供参考电压。如ADC. DAC, CMP.EditbyiliE:soonli@qq.com
- 2020-12-06下载
- 积分：1
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无损直播录制工具
欢迎使用Live-DL保存直播，本工具通过FFmpeg保存直播流，CPU占用极低。支持录制所有RTMP方式推流的直播网站，如哔哩哔哩等Step1.复制直播流地址到窗口（直播流地址可以通过Chrome浏览器F12“检查”功能获得，切换到Network选项卡，刷新页面，最长的一条就是）Step2.输入保存的文件名（文件会保存为“当天日期+你输入的名字.mp4”）Step3.选择保存路径a.保存在当前文件夹 b.保存在E:ReliveSave c.自定义路径（例如C:usersyournamedesktop）按Q可停止
- 2020-12-08下载
- 积分：1
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在NI LabVIEW 环境中使用Agilent GPIB解决方案的应用提示
讲述Labview操作Agilent GPIB的条件及需要安装的软件
- 2020-12-07下载
- 积分：1
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WIFI智能家居控制系统源码
WIFI智能家居控制系统
- 2021-05-06下载
- 积分：1
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纯C++实现bmp图片旋转
不调用库函数，纯C++实现灰度bmp任意尺寸图片的任意角度旋转~~~~采用最邻近插值法~~
- 2021-05-07下载
- 积分：1
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PCIE PCI-E X16的金手指和插座的3D 立体PCB封装 模板，AD DXP
PCIE-16x 的Altium PCB封装， 包含 金手指 封装 和 插座封装， 3D模型，不是平面的，PCIE-X16.PcbLib，可用Altium Designer打开
- 2020-12-05下载
- 积分：1
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PCI Specification 3.0_PCI 3.0 规范
PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0PCI LOCAL BUS SPECIFICATION, REV.3.0ContentsPREFACESPECIFICATION.……13INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)1查音音鲁垂音音13DOCUMENT CONVENTIONS.………14l. INTRODUCTION…151.1. SPECIFICATION CONTENTS······151.2. MOTIVATION……151.3. PCI LOCAL BUS APPLICATIONS1. 4. PCI LOCAL BUS OVERVIEW171.5. PCI LOCAL BUS FEATURES AND BENEFITS……181. 6. ADMINISTRATION…………………202. SIGNAL DEFINITION m...mn.. 212.1 SIGNAL TYPE DEFINITION222.2. PIN FUNCTIONAL GROUPS..…………222.2.1. System Pins……,…,…,,…,…232.2.2. Address and data pins242.2.3. Interface Control Pins........................252.2.4. Arbitration Pins(Bus Masters Only)272.2.5. Error Reporting Pins....垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂272.2.6. Interrupt Pins( Optional)……282.2.7. Additional signals312.2.8.64- Bit bus extension pins( Optiona)…,,……………………………332.2.9. TAG/Boundary scan Pins(Optional).......342. 10. System Management Bus Interface Pins(Optional)352. 3. SIDEBAND SIGNALS362. 4. CENTRAL RESOURCE FUNCTIONS.····:·····.·············363. BUS OPERATION373.1 BUS COMMANDS373.1. Command definition373. 1.2. Command Usage rules393.2. PCI PROTOCOL FUNDAMENTALS423.2.1. Basic Transfer Control····:············.················433.2.2. Addressing.............143.2.3. Byle lane and Byte enable usage……563.2.4. Bus Driving and Turnaround非音垂垂·非573.2.5. Transaction Ordering and posting….583. 2.6. Combining Merging, and Collapsing。。音垂。音62PCI LOCAL BUS SPECIFICATION, REV.3.03.3. BUS TRANSACTIONS……643.3.1. Read transaction……………653.3.2. Write transaction3.3.3. Transaction termination.………….673.4. ARBItRAtION音垂3.4.1. Arbitration Signaling protoco1..…………………893.4.2. Fast Back-to-Back Transactions. .........................................................93.4.3. Arbitration Parking………………………………………93.5 LATENCY953.5.1. Target Latency…….953.5.2. Master Data latency……….….…….,….….…..……..….,983.5.3. Memory Write Maximum Completion Time limit3.5.4. Arbitration Latency3.6. OTHER BUS OPERATIONS……·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非1103.6.1. Device selection…....…,103.6.2. Special cycle...........3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,…1133.6.4. Interrupt acknowledg3.7. ERROR FUNCTIONS春音·。音垂1153.7.. Parity ger1153.7.2. Parity Checking...........………,163.7.3. Address parity errors…...…,…163.7.4.Error Reporting…17173.7.5. Delayed Transactions and Data Parity Errors.......... 203.7.6. Error Recovery.............,213. 8. 64-BIT BUS EXTENSION1233.8.1. Determining bus Width during System initialization.…….…,1263.9.64- BIT ADDRESSING…..…………………………………………1273.10SPECIAL DESIGN CONSIDERATIONS.1304. ELECTRICAL SPECIFICATION.. m.m.9.1374.1. OVERVIEW…1374.1.1. Transition Road Map……1374.1.2. Dynamic vs Static Drive specificalion…1384.2. COMPONENT SPECIFICATION.……,………………,1…………………1394.2.1. 5V Signaling environment1404.2.2. 33V Signaling environment鲁鲁·垂垂1464.2.3. Timing specification1504.2.4.1determinate Inputs and metastable作,…………1554.2.5. Vendor provided specification..,..…,.…………….………17564.2.6. Pinout recommendation157PCI LOCAL BUS SPECIFICATION. REV.3.04.3. SYSTEM BOARD SPECIFICATION.………1584.3.1. Clock skew,…………………1584.3.2.R··1584.3.3. Pull-ups:····.················:·····…1614.3.4Power1634.3.5. System Timing Budget. ...........1644.3.6. Physical requirements............………674.3.7. Connector Pin assignments……/6844. ADD-IN CARD SPECIFICATION1714.4.1.Add- in Card Pin Assignment..,.,.,………………,1714.4.2. Power Requirements….,.,.,.,.,.,.,,.….,764.4.3. Physical requirements.........1785. MECHANICAL SPECIFICATION1815.1. OVERVIEW1812. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........1825.3. CONNECTOR PHYSICAL DESCRIPTION…………………1954. CONNECTOR PHYSICAL REQUIREMENTS. ...............................2055. CONNECTOR PERFORMANCE SPECIFICATION……………,…2066. SYSTEM BOARD IMPLEMENTATION……………2076. CONFIGURATION SPACEb●看●鲁D鲁0e●2136. 1. CONFIGURATION SPACE ORGANIZATION音垂垂D·垂看垂…2136.2. CONFIGURATION SPACE FUNCTIONS .......................2166.2.1. Device ldentification鲁垂垂2166.2.2. Device Control鲁着鲁D垂2176.2.3. Device status2196. 2.4. Miscellaneous registers·······:········:···:·:··:·:······:··············4······:····2216.2.5. Base addresses……………………….22463. PCI EXPANSION ROMS2286.4. VITAL PRODUCT DATA.2296.5. DEVICE DRIVERS2296.6. SYSTEM RESET.…………………………2306.7. CAPABILITIES LIST2308. MESSAGE SIGNALED INTERRUPTS ...................................................................2316.8.1. MSI Capability Structure..............2326.8.2. MSl-X Capability and Table structures……………….……..2386.8.3. MSI and Msi-X Operation2467. 66 MHZ PCI SPECIFICATION2557. 1. INTRODUCTION2557.2. SCOPE7. 3. DEVICE IMPI TION CONSIDERATIONS7.3.1. Configuration space.......2557. 4. AGENT ARCHITECTURE256PCI LOCAL BUS SPECIFICATION, REV.3.07.5. PROTOCOL.……2567.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,2567.52Latency..-..-.-2577.6. ELECTRICAL SPECIFICATION……………2577.6.. Overview·.·······.··2577.6.2. Transition roadmap to 66 MHz PCI··········.2577.6.3. Signaling Environment.......... 2587.6.4. Timing specification.……2597.6.5. Vendor provided specification. 26.57.6.6. Recommendations·.·························:············:······:········.:··········2657.7. SYSTEM BOARD SPECIFICATION.………,…,……………2667.7.1. Clock Uncertainty ......2667.7.2. Reset2677.7.3. Pullups..2677.7.4. Power..······.·.·::·····布鲁····音D鲁番。是。音垂看····非D∴2677.7.5. System Timing Budget7.7.6. Physical requirements2687.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,2697.8. ADD-IN CARD SPECIFICATIONS春音·。音垂2698. SYSTEM SUPPORT FOR SMBUSn2718. 1. SMBUS SYSTEM REQUIREMENTS2718.1.1. Power………278. 2. Physical and Logical sMBi27l8.1.3. Bus connectivit2728.1.4. Master and slave support....….….…..…..…..,2738.1.5. Addressing and Configuration2738.1.6.Ele2748.1.7. SMBus behavior on Pcl reset.........................2748.2.ADD- IN CARD SMBUS REQUIREMENTS…………2758.2.7Connection2758.2.2. Master and Slave Support...,.…..…….…,...….,2758.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,2758. 2. 4. Power2758. 2.5. Electrical.········.····························275A. SPECIAL CYCLE MESSAGES●鲁●e鲁277A 1. MESSAGE ENCODINGS277A,2. USE OF SPECIFIC ENCODINGS ................................................277B. STATE MACHINES279B. 1. TARGET LOCK MACHINE·;.···.:..···:...···:··.·:····281B.2. MASTER SEQUENCER MACHINE283B 3. MASTER6PCI LOCAL BUS SPECIFICATION. REV.3.0C. OPERATING RULES289C 1. WHEN SIGNALS ARE STABLE..·····.:·.·.::···:·;289C.2. MASTER SIGNALS…音·。·看290C.3. TARGET SIGNALS…291C.4. DATA PHASES…292C.5. ARBITRATION.……………………………………292C.6. LATeNCY······:“·······293C.7. DEVICE SELECTION……………,……………………………293C 8. PARITY垂垂垂D·垂294D. CLASS CODESD 1. BASE CLASS OOH...w.w...296D 2. BASE CLASS OlH296D. 3. BASE CLASS O2H··297D 4. BASE CLASS O3H297D.5. BASE CLASS04H.………………………298D. 6. BASE CLASS OSH298D.7. BASE CLASS06H...………….…………………299D 8. BASE CLASS OZH,300D 9. BASE CLASS OSH.301D.10. BASE CLASS C9H.……………………………………………….301D.11. BASE CLASS OAH.…………………302D 12. BASE CLASS OBH302D. 13. BASE CLASS OCH303D.14. BASE CLASS ODH….…304D. 15. BASE CLASS OEH304D. 16. BASE CLASS OFH·····.····;····:·;:·······304D.17. BASE CLASS JOH.……………………………………………1305D, 18. BASE CLASS 11H305E. SYSTEM TRANSACTION ORDERINGE.I. PRODUCER- CONSUMER ORDERING MODEL308E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS310E.3. ORDERING OF REQUESTS........................................311E.4. ORDERING OF DELAYED TRANSACTIONS…………312E.5. DELAYED TRANSACTIONS AND LOCK#.317E.6. ERROR CONDⅠ TIONS……318. EXCLUSIVE ACCESSES..m.msn0..319F.1. EXCLUSIVE ACCESSES ON PCIF 2. STARTING AN EXCLUSIVE ACCESS321F.3. CONTINUING AN EXCLUSIVE ACCESS323F 4. ACCESSING A LOCKED AGENT324F 5. COMPLETING AN EXCLUSIVE ACCESS325F. 6. COMPLETE BUS LOCK ......................................................................325IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327PCI LOCAL BUS SPECIFICATION, REV.3.0CAPABILITY IDS。,0329I. VITAL PRODUCT DATA331VPD FORMAT3I.2COMPATIBILITY……………………………334L.3. VPD DEFINITIONS3341.3.1. VPD Large and small resource Data Tags......·D垂看3341.3.2. VPD Example…3378PCI LOCAL BUS SPECIFICATION. REV.3.0FiquresFIGURE -I: PCI LOCAL BUS APPLICATIONS春DFIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM17FIGURE2-1: PCI PIN LIST.…………..…………21figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONSADDRESS PHASE51FIGURE3-4: CONFIGURATION READ…………156FIGURE3-5: BASIC READ OPERATION………………………65FIGURE 3-6: BASIC WRITE OPERATION66FIGure 3-7: MASTER INITIATED TERMINATION........................ 68FIGURE3-8: MASTER- ABORT TERMINATION…………69Figure 3-9: RETRY. ..........................................................................................................73FiGure 3-10: DISCONNECT WITH DATA. ........................74FiGure 3-11: MASTER COMPLETION TERMINATION:·:····:··.·4····.···…75FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION·····76Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION76FiGure 3-14: TARGET-ABORT…177figure 3-15: BASIC ARBITRATIONFIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS…94FiGurE 3-17: DEVSEL# AsSERTION·····:···.·:··110Figure 3-1 8: IDSEL STEPPING114FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114FIGURE3-20: PARITY OPERATION………116FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER125FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE129FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.…………………143FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling145FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING148FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150FIGURE 4-6: CLOCK WAVEFORMS151FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS.··4·:······.·154FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT···“···:.···.····:·········157FIGURE4-10: CLOCK SKEW DIAGRAM………158FIGURE 4-1: RESET TIMING16lFIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT).183FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186PCI LOCAL BUS SPECIFICATION, REV.3.0FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V)189FIGURE 5-8: PCI STANDARD BRACKET………190FIGuRE 5-9: PCI LOW PROFILE BRACKET191FIGURE 5-10: PCI STANDARD RETAINER···192FIGURE5-11: IO WINDOW HEIGHT∴………………193FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194FIGURE 5-13: 32-BIT CONNECTOR196FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197FIGURE5-15:3.3V/64-BIT CONNECTOR198FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES2(垂D·。垂,音着垂。着音D。。着。D音着音垂。音着音FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES….201FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES………………………………202FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES203FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204FIGURE5-22: CONNECTOR CONTACT DETAIL………………205FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD208FIGURE5-24:32- BIT PCI RISER CONNECTOR……209FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT210FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR211FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER215FIGURE 6-2: COMMAND REGISTER LAYOUT217FIGURE6-3: STATUS REGISTER LAYOUT……………………………219FIGURE 6-4: BIST REGISTER LAYOUT222FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O225鲁着D音看FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233FIGURE 6-10: MSI-X CAPABILITY STRUCTURE238FIGurE 6-11: MSI-X TABLE STRUCTURE翻音。音239FIGurE 6-12: MSI-X PBA STRUCTURE…239FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING······:··················257FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS263FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS263FIGURE75:TvAL(MAX) RISING EDGE…………264FIGURE 7-6: TVAL(MAX) FALLING EDGE·265FIGURE77:TVAL(MIN) AND SLEW RATE……26510
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室内三维定位算法，伸缩因子
matlab 室内三维定位算法，改进的Toa算法
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