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单载波频域均衡（SC-FDE）仿真
仿真比较了SC-FDE与OFDM均衡性能，包括LMS，Z-F算法，RLS算法。
- 2020-12-04下载
- 积分：1
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EKF,UKF,PF2 三种滤波算法的比较
完整的EKF,UKF,PF三种滤波算法的比较，包括状态估计，误差比较，和置信区间。
- 2020-11-29下载
- 积分：1
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华视CVR-100U身份证阅读器C#读取demo
华视CVR-100U身份证阅读器C#读取demo，可以读取身份证信息，身份证头像图片，32位API，自己亲测可用
- 2020-12-09下载
- 积分：1
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超全的模式识别Matlab源程序，涉及几乎所有常见算法，还有图形界面
超全的模式识别Matlab源程序，涉及几乎所有常见算法，还有图形界面
- 2020-11-29下载
- 积分：1
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Winform中使用CefSharp和js互相调用方法
Winform中使用CefSharp和js互相调用方法，Winform中使用CefSharp和js互相调用方法，Winform中使用CefSharp和js互相调用方法，Winform中使用CefSharp和js互相调用方法vs2019.debug目录下有cef所需要的文件，在其他项目里可以直接拷贝过去
- 2020-11-29下载
- 积分：1
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VC++ 共享内存读写操作
此解决方案含两个工程文件，一个是写操作工程文件，即把任意字符串写入创建的共享内存里，另外一个读操作工程文件，则是读取共享内存里的数据，从而实现了进程之间的共享内存读写操作。
- 2020-12-04下载
- 积分：1
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养老院管理系统.rar
养老院管理系统代码，使用的mysql数据库:https://download.csdn.net/download/weixin_40490238/11484946
- 2020-11-27下载
- 积分：1
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verilog_IEEE官方标准手册-2005_IEEE_P1364
The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group
- 2020-12-11下载
- 积分：1
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96-Site_DKA-MasterMeter1.csv.gz
该数据是澳大利亚太阳能研发中心的光伏发电功率数据，包括发电功率，风速，光照，降雨量，温度，湿度等影响因子。可以用于个人研究，模型训练，毕业设计等
- 2021-05-07下载
- 积分：1
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解释结构建模
MATLAB程序对任意规模的关联图进行ISM计算，自定义输入数据格式和输入方法，输出元素分层结果、对应的骨架矩阵以及所有的关联回路，
- 2020-11-27下载
- 积分：1
