Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. While the ieee administers the processand establishes rules to promote fairness in the consensus development process, the ieee does not independentlyevaluate, test, or verify the accuracy of any of the information contained in its standards.Use of an IEEE Standard is wholly voluntary. The ieee disclaims liability for any personal injury, property orother damage of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly orindirectly resulting from the publication, use of, or reliance upon this, or any other iEEE Standard documentThe ieee does not warrant or represent the accuracy or content of the material contained herein, and expresslydisclaims any express or implied warranTy, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement. 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Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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RK3229 MIC
RK3229 的多mic阵列麦方案，RK原厂提供，对于做多MIC客户用途比较大RaCkChpP瑞芯微电子福州瑞芯微电子股份有限公司目录目录3概述■1■■1■■1■1■■1■■1■1面■■■■■■4产品版本4适用对象41-概述,:■:■":■::■::::::::::::.::.::.::.::.::::":::::::::::::::::::1.1麦克风阵列EK廾发平台简介1.2麦克风阵列EVK框图.13麦克风阵列E∨K组件2麦克风阵列E硎K介绍..………82.1整体效果图82.2结构与接口示意图3麦克风阵列子板模块简述n113.16+0+2麦克风阵列方案说明113.2内、外圈园周阵列麦■重着国面重着国面重着国面日重面重面重面自重面自■重■,面■重■面■重■,面重■,面■113.3 Codec.3.4PA133.5 Loopback回采电路,,,,,,,,,133.6排针∴144注意事项∴.….154.1注意事项15Copyright 2015 @Fuzhou Rockchip Electronics Co., LtdRaCkChpP瑞芯微电子福州瑞芯微电子股份有限公司前言概述本文档主要介纽RK麦克风阵列EVK基本功能特点和硬件特性、硬件配置以及使用方法,旨在帮助相关开发人员更快、更准确地使用该EVK,进行麦克风阵列冫案的应用开发E∨K由RK3229主板与麦克风阵列子板共两部分组成,本文档着重介绍麦克风阵列相关内容,即麦克风阵列」板及其与RK3229主板相关联部分。涉及RK3229主板的其他功能,可参考《RK3229BOX开发板用户使用指南》以获取更详细信息。产品版本本文档对应的产品版本如下:品名称版本描述RK SDK BOX RK3229 Discrete PowerV1.0RK3229主板DDR3P416DD6V1020160120LⅩFRK BOX EVB MICARRAYTESTBOARDV1.06+0+2麦克风阵列子板RK3229V1020160901适用对象本文档主要适用于以下人员:技术支持工程师单板硬件开发工程师频算法工程师嵌入式软件开发工稈师测试工程师Copyright 2015 @Fuzhou Rockchip Electronics Co., LtdRaCkChpP瑞芯微电子福州瑞芯微电子股份有限公司缩略语缩略语指文档中常用的词组简称:内部整合电路(两线式串行通讯总I2CInter-Integrated Circuit线)I2SInter-IC Sound集成电路内置音频总线PAPowerAmplifier此处特指音频功率放大器RKRockchip lectronics Co. Ltd瑞芯微电子有限公司Copyright 2015 @Fuzhou Rockchip Electronics Co., LtdRaCkChpP瑞芯微电子福州瑞芯微电子股份有限公司1概述1.1麦克风阵列EVK开发平台简介RK3229芯片是一款包括NeOn和FPU协处理器在内的四核 ARM Cortex-A7处理器,主频1.5GHz;集成∫32 bits ddr3/DDR3L/ LPDDR2/ LPDDR3控制器,提供了高性能、髙分辨率应用程序所需要的内存带宽。芯片能胜任高分辨率(4K/60Hz)显示、多通道(8+2)音频处理和主流应用。芯片内置3路I2S接口,I2S1用于HDMI输出的音频处理,另外2路I2S0与I2S2可供用户自由分配。其中,I2S2支持同吋2通道输入与2通道输出,I2S0则可最扃支持至8通道输入或8通道输出。麦克风阵列E∨K是基于6+0+2名麦克风方案(6+0+2介绍见3.1章节)的硬件参考设计,同时RK3229主板将芯片资源都作了引出,方便客户验证、调试与二次开发,只需要简单修改参考设计的模块电路,就可以完成产品的硬件设计12麦克风阵列EvK框图RK3229主板使用12∨/2A适配器供电,通过UART串口进行调试,验证各功能模块。开发板配有HDMI输出, SPDIF输出,ⅥWIFI+BT模组, Etherne接口,USB接口,TF卡,红外接收以IR,CVBS视频接口等,非常有利于芯片方案的深入研发与快速产品化。主板与麦克风阵列子板通过10x2的2.54mm排线连接,音频接口包括5V电溟、1组I2S1信号、1组I2C信号与2个通用GPIO。详细资源使用情况见下图:Copyright 2015 @Fuzhou Rockchip Electronics Co., LtdRaCkChpP瑞芯微电子福州瑞芯微电子股份有限公司口RockchipRK3229Serug OARI2wskur Reset nimrod4x二C/D2XLDOPowerUSB HUST2J图1RK3229主板系统框图工C3Vf∞rMICaD5V王CC⊥K工CM工c5图2麦克风阵列子板系统框图13麦克风阵列EvK组件麦克风阵列EWK主要包括以下物品:RK3229主板麦克风阵列子板电源适配器,规格:输入100VAC240VAC,50;输出12VDC,2A2.54m20针排线Copyright 2015 @Fuzhou Rockchip Electronics Co., LtdRaCkChpP瑞芯微电子福州瑞芯微电子股份有限公司2麦克风阵列EW介绍2.1整体效果图麦克风阵列EWK整体实物图如下ppDJoZl (l esnw最w箱x思图1麦克风阵列EVK实物图Copyright 2015 @Fuzhou Rockchip Electronics Co., LtdRaCkChpP瑞芯微电子福州瑞芯微电子股份有限公司g88888图2麦克风阵列子板实物图-正面、背面2.2结构与接口示意图麦克风阵列了板PB布局如图所示外园麦克风、6个直径Rcm闪园麦先风、6个直径5cmCodecPAT排针Codec(6PA2喇刺叭翰出2RK BOX EVB NICARRAY TESTBOARD RK3226_2018%ad图5麦克风阵列子板PCB正面图Copyright 2015 @Fuzhou Rockchip Electronics Co., LtdRaCkChpP瑞芯微电子福州瑞芯微电子股份有限公司各模块及接∏说明如卜表表1麦克风阵列子板说明编号说明措述1选项1-外圈麦克风直径80mm6个数字麦克风2选项2-内圈麦克风直径50mm6个数字麦克风选3odec每个 Codec支持2路输出与2路输入PAD类音频功放芯片456喇叭输出2个喇叭输出排针与RK3229主板连接的排针Copyright 2015 @Fuzhou Rockchip Electronics Co., Ltd10
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