Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. 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Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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基于MATLAB的指纹识别系统设计
基于MATLAB的指纹识别系统设计论文，具有一定参考价值，对毕业设计有用。基于 MATLAB的指纹识别系统设计AbstractBiometric technology has become one of the developing technologies for identityrecognition and network security. And fingerprint identification technology is now recognizedas one of the most safe. accurate and convenient authentication technologies and it is a focusfor researchersThis paper designs a matlab-based fingerprint recognition system. The first introducesthe fingerprint recognition technology research background, significance, and the status quoSecondly, to achieve fingerprint identification system, describes the basic structure of thefingerprint identification system, and the fingerprint image preprocessing, feature extractionfeature matching these three essential aspects of the algorithm is studied in detail in thefingerprint image pre-processing stage this article uses an algorithm based on gray imagesegmentation carried out at the same time, for the image after binarization noise still existsbut also for the corresponding trimming process, as much as possible for the future lay thefoundation for fingerprint feature extraction and thus successfully achieved fingerprint digitalimage processing, Teature extraction, slorage and matching functions. Finally, Che fingerprintidentification system for simulation, simulation results show that the system can identify abetter accuracy rate reached 95.1%Key Words: Fingerprint Recognition; Processing; Binarization; Feature Extraction;Feature Matching基于 MATLAB的指纹识别系统设计目录摘要······*······················-·······“······“···+····“····“““··“···············*·····““·········Abstract1绪论1.1本课题背景和意义1.2指纹识别技术研究现状1.3本文的章节安排中中中·中中和中。中申中申中中中非和申中日…22指纹识系统设计42.1指纹识别系统设计基本结构.42.2指纹图像分割…2.2.1指纹图像分割介绍2.2.2均值方差法2.3指纹图像的细化…2.3.1指纹图像细化的预处理2.3.2指纹图像细化方法计算72.4指纹图像的特征提取…2.4.1指纹特征提取概述着非非非道非非非非自非非非非日非着非非非非非非2.4.2指纹特征提取和去伪特征2.5指纹图像匹配方法……102.5.1指纹图像匹配介绍…26本章小结3仿真结果及其分析3.1仿真结果及分析…123.2本章小结…,14结论参考文献.17附录 MATLAB程序m重自18致谢“···*:····35IlI基于 MATLAB的指纹识别系统设计1绪论1.1本课题背景和意义指纹识別技术的应用十分广泛,指纹因具有终生不变性及稳定性,而且不同人指纹相同的概率儿乎为零,因此指纹自动识别系统被广泛应用于案例分析、商业活动中的身份鉴别等领域.目前有很多的生物测定技术可用于身份认证,包括虹膜识别技术、视网膜识别技术、面部识別、签名识别、声音识别技术、指纹识別等,具有安全、可靠的特点,其中自动指纹识别系统是目前研究最多、最有应用前景的生物识别系统。指纹识别技术的发展得益于现代电子集成制造技术的进步和快速可靠的算法的研究。指纹门禁系统通过将用户的指纹特征与指纹特征数据库屮的数据进行对比实现用户身份的鉴别,并不直接保存和使用用户的指纹图像信息,不会侵犯到用户的隐私信息,是当前技术最先进、应用最广泛的门禁系统。对生物识别(指纹识别)技术来说,被广泛应用意味着它能在影响亿万人的日常生活的各个地方使用。通过取代个人识别码和口令,生物识别(指纹识别)技术可以阻止非授权的“访问”;可以防止盗用ATM、蜂窝电话、智能卡、桌面PC、工作站及其计算机网终;在通过电话、网络进行的金融交易时进行身份认证;在建筑物或工作场所生物识别技术(指纹识别)可以取代钥匙、证件、图章等。生物识别(指纹识别)技术的飞速发展及其广泛应用将开创个人身份鉴别的新时代。指纹所具有的唯一性、不变性、及易于获取、分类存储有规律等特性使其成为生物鉴定学中最为成熟的方式。1.2指纹识别技术研究现状指纹识别技术从早期的人工比对到现在采用计算机技术实现自动指纹识别,指纹对比更加准确,识别效率得到极大提高。自动指纹识别过稈通常由指纹图像滤波增强、二值化、细化、征提取以及指纹匹配等几个环节构成。指纹图像滤波增强的目的是将有噪声干扰的指纹图像变得更加清晰,使得指纹图像的脊线更黑,谷线更白,当前在实际指纹图像増强算法的应用中一般是几种滤波增强方式结合起来使用,主要的方案是基于傅里叶变换结合滤波和指纹图像点方向场的下上下滤波器;指纹图像二值化,是将指纹图像变成灰度值只有0和255两种颜色的图像,当前,在自动指纹识别中棠用的是根据指纹图像的点方向场在指纹纹线方向和指纹纹线垂直方向上对指纹图像进行一值化处理;指纹图傻细化是指删除指纹纹线的边缘像素,使之只有一个像素宽度,目前在自动指纹识别技术中常用的是OPIA算法的改进的图像模板细化算法;指纹特征提取,是将细化后使用计算教字图像处理技术采集指纹图像中奇异点、端点、叉点等指纹特征基于 MATLAB的指纹识别系统设计数据,目前常用的特征提取算法是先对细化后的指纹图像进行初步去噪,然后提取特征点,再根据阈偵去除伪特征点:指纹匹配,是指纹预留模板图像与输入样板图像中的所有特征点的匹配,目前在自动指纹识别系统中常采用可变大小的界限盒的指纹特征匹配算法。目前指纹识别技术还有诸多困难,例当三维的指纹被指纹录入设备扫描成二维的数字图像时,就会丢失一部分信息,手指划破、割伤、弄脏、不同干湿程度以及不同的按压方式,还会导致指纹图像的变化,这就给可靠的特征提取带来了困难;例如传统的基于细节点的识别方法,是依靠提取指纹脊线上的细节点,然后对其位置和类型进行匹配,来识别指纹的,而噪声会影响特征提取准确度,增加错误的特征点或丢失真正的特征点。当噪声很大时,就要增加图像增强算法来改善图像的质量,但很难找到一种增强算法能够适应所用的噪声,多种増强算法又会人嗝増加算法运行时间,不好的増强算法又会增加人为特征。当喉声增大时,提取了许多虚假细节点,还有可能丢失细节点,这就是传统的基于细节点识别算法的不足之处之一,因为它只利用了指纹图像中的一小部分信息(细节点位置和方向)作为特征进行匹配,丢失了蕴涵在图像中的其他丰富的结构信息。不难想象,基于这种方法的识别算法,很难个面适应指纹的变化。人的指纹含有天然的密码信息,它们具有几点重要特特点①广泛性,指每一个正常的人都有指纹。②唯一性,指每一个人的指纹都不同。指纹的纽节由细微纹点和纹线的起点、终点、分叉等组成。止是这些无穷无尽的细节特征组合构成了指纹的唯一性,事实上,甚至包括双胞胎,世界上两个指纹相同的概率小于1/109,几乎为零,这就构成了指纹的第大特点。③终生不变性,指纹终身不变即指纹的图案永远不会改变,从人的出现到死后的分解为止(除非指纹受到伤害)。④指纹与主体的不可分离性:即指纹不存在丢失、遗忘、被窃取的可能。指纹的使用比起其它证卡来说更快捷、安全、准确、无干扰,可实现快速登录注册,系统兼容性好,也就是说可以独立或者通讨联网构成系统并H很容易并入各类证卡和定义识别系统中。因此,指纹识别技术的应用范围极广。1.3本文的章节安排本文以研究指纹识别中指纹图像分割、细化、特征提取、匹配等若十问题为研究主体,针对指纹识别技术中分割、细化和匹配进行了仿真和修正。其中分割部分采用了方基于 MATLAB的指纹识别系统设计差均值的方法,细化选取了一种伪特征较少的模板,匹配时以分叉点和端点信息进行匹配。具体的章节和各章的内容安排如下:第一章:在介绍本论文的研究背景及意义,在指纹识别技术的现状和特点的基础上,确定了本文所做的主要工作。第二章:本章主要介绍了指纹识别系统设计原理,为后续的研究工作奠定基础,介绍了均值方差的基础知识和基本理论以及仿真中具体的分割运用算法;指纹图像细化的方法;指纹图像细化后的特征提取,需要哪些特征,去除哪些伪特征,以方便和正确地进行匹配工作:指纹图像配的概念、匹配问题的困难所在和常用方法。第三章:指纹识别系统的仿真结果及分析。结论:总结本文所取得的一些研究成果,并对课题发展进行了展望。基于 MATLAB的指纹识别系统设计2指纹识系统设计2.1指纹识别系统设计基本结构指纹识別系统主要由指纹图像读取,图像预处理,特征提取,特征匹配四大步骤组成首先,我们要提取需要处理的指纹识别的原始图片。其次,进行图像预处理。通常图像预处理包括分割、归一化、二值化和细化,图像预处理的目的貮是去除图像中的噪声,将图像变成清晰点线图,这样才能提取到正确的指纹特征,从而达到止确匹配的目的。它的好坏直接影响到指纹识别的效果。在此基础上,接下来就是要对细化后的数字图像进行关键特征提取,从而达到识别不同的志文数字图像的目的。普遍采用的特征提取是提取细节点。最后,我们将处理后的图像进行匹配,指纹图像的特征匹配主要是对所提取的细节持征进行匹配,将要比对的图像与库中图像的细节特征进行比对,并将比对结果输出,这是指纹识别系统设计中最重要的一个环节,这也是指纹识别系的最终目的。2.2指纹图像分割2.2.1指纹图像分割介绍指纹图像分割在指纹识别系统中作为图像与处理的一部分,指纹图像分割的基本依据是图像的某些特征及特征的集合。如灰度值,邻域关系,纹线的扭曲程度等。图像特征是指纹图像的怗有属性。通过提取图像特征,可将原始图像映射到特征空间,使图像特征在特征空间中呈现一定的分布。因此根据以上的的灰度值领域关系,纹线的扭曲程度,指纹图像分割大致分为三类:基于像素的图像分割,基于块特征的图像分割以及基于全局的图像分割。基于像素的指纹图像分割中目前流行多尺度小波变换和阙值法。小波变换和傅里叶变换的出发点都是将信号表示成基函数的线性组合。所不同的是傅里叶变换采用时间属于(一∞,+∞)的谐波函数exP@x作为基函数,计算机中的图像信息是以离散信号形式存放的,在信号处理中,特别是在数字信号处理和数值计算等方面,为了计算机实现的方便,连续小波必须进行离散化,而最基本的离散化方法就是二进制离散,一般将这种经过离散化的小波及其变换叫做二进小波和进变换。基于 MATLAB的指纹识别系统设计小波变换的特点是压缩比高,压缩速度快,压缩后能俣持信号与图象的特征不变,且在传递中可以抗干扰。在指纹识别识别中使用小波变换有助于噪卢的滤除以及有利于检测奇异点。但是小波变換的明显缺点是它计算复杂,计算效果也取决于函数的选择。另一种阙值分割就是简单地用一个或几个阈值将图像的灰度直方图分成几个类,认为图像中灰度在同一个灰度类内的像素属同一物体。它是图像分割中最基本的方法。其原理是先定一个阈值,大于此值为1,小于则认为为0;多阀值则可以利用多维函数。此原理在匹配中也可以运用。其优点是计算简单,仅需比较灰度值即可;运算效率较高,速度快:它的缺陷在于仅考虑图像的灰度信息,而忽略了图像的空间信息,对于图像中不存在明显灰度差异或各物体的灰度值范围有较大票叠的图像分割问题难以得到准确的结果代表块特征的指纹图像分割日前研究趋势为多种块基本特征如灰度均值、块灰度方差、块方向图等综合运用和重新定义块特征。其中块指的是将图像分个成一个个小的图像块。图像均值就是对每个单位块的灰度值取均值,方差则反映该块中各点与均值的偏差性,方向这可以很好的反映纹理的变化趋势。一般来说,常见的方向场的计算分为掩模法和公式法两大类。 LinHong等人开发的基于最小均方估计算法,即公式法。(j)=G(-1,j-1)+2G(-1)+G(+1j-1)-G(-1,+1)-2G(1,j+1)-G(i+1,+1)(j)=G(-1,j-1)+2G(+1)+G(-1,+1)-G(i+1,-1)-2G(i+1,j)-G(i+1,j+1Rx(∴j)(,(a,v)(,y)2-a(x,y)2它是利用正交坐标系下,原点到它们组成的坐标点的有向线段与X的正半轴的夹角可来表示该子块的块方向。这种方法最人的优点是易实现,很好体现出纹理,但缺点是对于变化太快的部分出错。此方法的实现是利用方向滤波器。基于全局的图像分割则是根据情況特别是某些特殊场合的利用,如残缺指纹。全局的图像分割可以是人工选定几个特定点后再根据全局的特点来处理,此法也可运用于匹配。基于全局的指纹识别仍处于实验室探索阶段,应用领域中尚不广泛。2.2.2均值方差法在图像分割概述中,凵经提到基于块特征的指纹图像分割。在这部分将重点介绍均值法差法的计算方法和在仿真中的运用基于 MATLAB的指纹识别系统设计该算法基于背景区灰度方差小,而指纹区方差大的思想,将指纹图像分成块,计算每一块的方差,如果该块的方差小于阈值为背景,否则为前景。具体步骤分以下三步(1)将低频图分成MXM大小的无重叠方块,方块的大小以一谷一脊为宜。(2)计算出每一块的均值和方差。H-1L-AVe=B2∑(.R=_1台台2>>(,)-4VE)(3)如果计算得到的方差几乎接近于0就认为是背景,对于方差不为零的区域在进行阈值分割算法,这种算法主要是根据计算得到的方差来决定其是否为背景区在使用方差均值法之前还要使用归一法将图变为低频图。归一化的目的是把不同原图像的对比度和灰度调整到一个固定的级别上,为后续处理提供一个较为统一的图像规格。指纹图像的归‘化公式如式所示。其中AVE0和ⅤAR为期望的灰度均值和方差。但是小波变换的明显缺点是它计算复杂,计算效果也取决于函数的选择。Rol/(x, ?)-AVENAV点o+lvARo(/(x, -AVEY(3.3)AVEoVAR在使用方差均值法之前还要使用归一法将图变为低频图。归一化的目的是把不同原图像的对比度和灰度调整到一个固定的级别上,为后续处理提供一个较为统一的图像规格。2.3指纹图像的细化2.3.1指纹图像细化的预处理这部分预处理主要为_二值化。由于指纹图像脊、谷相间,因此指纹图像的处理常是将指纹图像一值化。灰度图像一值化是将灰度图变换为只有黑和白两种灰度的图像。这样不仅可以压缩原指纹图像的数据量,而且也方便后面的细节特征的提取。灰度图二值化的基本思想是选取适当的灰度阂值,将灰度图像转化为_值图像,阈值的选择是关键,对于阈值的选择,有多和方法,如熵法,stu法等。根据是否将图像分块处理,又分全
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