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LZ77_1
Package include hardware implementation of Lz77 algorithm
- 2021-04-26 10:38:45下载
- 积分:1
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VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)
VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)
- 2022-01-27 10:40:51下载
- 积分:1
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ep2c5 实现 段寄存器,实验一
verilog语言,quartus 2 仿真
ep2c5 实现 段寄存器,实验一
verilog语言,quartus 2 仿真-Register ep2c5 achieve above experiment a verilog language, quartus 2 Simulation
- 2022-03-19 07:48:20下载
- 积分:1
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yinpin_display0925
实现音频的I2S通信,音频柱的显示,及其噪声的处理等功能(Realization of audio I2S communications, audio column display, and its noise processing, and other functions)
- 2016-01-07 10:08:31下载
- 积分:1
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Xilinx FPGA moving data across asynchronous clock boundaries
Xilinx FPGA moving data across asynchronous clock boundaries
- 2022-03-05 12:30:25下载
- 积分:1
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kouyu
考研复试口语,适合计算机专业考研复试口语专业课(Traditional Interview spoken, spoken for Specialized Computer Traditional Interview)
- 2011-04-26 16:05:11下载
- 积分:1
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LPC总线从设备的verilog设计,包含状态机和中断功能。
LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
- 2022-01-28 17:10:12下载
- 积分:1
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Synopsys使用基本步骤使用的集成工具,有用的好东西
使用synopsys的基本步骤,综合工具的使用说明,有用的好东西-Synopsys using the basic steps to use the integrated tools, useful good things
- 2022-04-06 15:39:11下载
- 积分:1
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rs-decoder-make-byvhdl
- RS码是Reed-Solomon 码(理德-所罗门码)的简称,它是一类非二进制BCH码,在RS码中,输入信号分成k·m比特一组,每组包括k个符号,每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)
- 2021-04-28 15:58:44下载
- 积分:1
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VHDL
产生svpwm波形,可以参考下载,以便学习交流(gennerate SVPWM wave)
- 2017-11-21 15:38:29下载
- 积分:1