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Verilog--HDL
本书是一本关于VERILOG方面的专业书籍,是通往FPGA设计的基础书籍,值得一看。(thsi is a book of VerilogHDL,also a basic book to master.)
- 2016-07-31 13:44:09下载
- 积分:1
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华勒斯树结构的8位修正展位乘数
应用背景Booth乘法器实现快速乘法algorithm.mainly用于通信和DSP组成的3块摊位重新编码,华勒斯树和超前进位addder关键技术超大规模集成电路设计,通信和DSP的应用,芯片设计,VHDL,Verilog程序,加法器和乘法器
- 2022-02-04 19:57:10下载
- 积分:1
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example
一个电子秒表,最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)
- 2013-12-17 12:28:14下载
- 积分:1
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snake
贪吃蛇程序,用verilog实现,可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)
- 2016-01-16 21:11:14下载
- 积分:1
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cycle_measure
测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)
- 2013-08-29 16:09:17下载
- 积分:1
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cycloneII ep2c5 ep2c8
cycloneII ep2c5 ep2c8
- 2022-06-26 08:54:36下载
- 积分:1
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cnt60
60进制计数器,(由一六进制和十进制连线组成)(60 binary counter (hexadecimal and decimal by a connection form))
- 2011-11-29 10:48:37下载
- 积分:1
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sanjose_hdlcon
FFT implementation using C program
- 2014-02-11 21:01:40下载
- 积分:1
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1553B的编解码程序是有用的给大家分享分享
1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share
- 2022-07-28 09:59:52下载
- 积分:1
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Verilog_add_div_multi_exp
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数,迭代次数(可设置)决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)
- 2020-12-18 09:49:10下载
- 积分:1