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CPU_Verilog
此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
- 2017-07-06 19:45:33下载
- 积分：1
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FPGA_four_num_code_lock
说明： 基于EasyFPGA030的四位数字密码锁。(Based on the four-digit lock EasyFPGA030.)
- 2010-04-29 15:16:29下载
- 积分：1
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PUF_TRNG
this is a verilog code of true random number generator using butterfly puf
- 2017-04-22 05:10:25下载
- 积分：1
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VHDL example, there are nearly a hundred examples, can be carried out in quartur...
VHDL实例,有近百个实例,都是可以在quarturs 上进行仿真的,大部分都可以通过,对初学者是一非常不错的-VHDL example, there are nearly a hundred examples, can be carried out in quarturs simulation, most of them can pass, for beginners is a very good
- 2022-04-16 23:40:20下载
- 积分：1
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5
fpga paper function fff(fpga paper function)
- 2010-03-11 23:15:24下载
- 积分：1
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控制ADV212 压缩的源代码 使用xilinx edk开发环境
控制ADV212 压缩的源代码 使用xilinx edk开发环境(adv 212 controller, using xilinx edk)
- 2020-06-27 03:40:01下载
- 积分：1
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ug835-vivado-tcl-commands
说明： Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
- 2020-10-26 22:50:00下载
- 积分：1
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6. For the key to enter a password lock, assuming that reset after the seven lam...
6对于进入密码锁的按键，假设复位后七个灯显示" 0"，使用sw1、sw2 2，然后只要按下并松开sw2，七个灯上就显示" 2"，而只要按下并松开sw1，七个灯上就正确显示值" 1
- 2022-03-11 23:10:49下载
- 积分：1
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base_4_fft
基4FFT原理及MATLAB实现，基本原理，编程思想等(base——4 FFT principle and MATLAB implementation, the basic principles of programming ideas, etc.)
- 2016-01-28 16:52:37下载
- 积分：1
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the-verilog-code-of-can-usb-i2c
CAN总线，I2C，USB等的FPGA实现源码(CAN bus, I2C, USB, etc. FPGA implementation source)
- 2012-12-15 01:25:33下载
- 积分：1
