-
verilog
数字信号除了的FPGA实现的Verilog源代码,之前发过一份是VHDL,各有所需吧,需要的看看吧(Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it
)
- 2012-02-25 15:06:35下载
- 积分:1
-
clock_6
ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
- 2020-06-24 12:00:02下载
- 积分:1
-
hard
在Quartus中,利用FPGA例化的存储器实现程序的BOOTLOADER的搬移(In Quartus, the use of FPGA case of memory to achieve the program' s move BOOTLOADER)
- 2020-09-27 20:17:46下载
- 积分:1
-
BGM benchmark
// DEFINES
`define BITS 32 // Bit width of the operands
`define NumPath 34
module bgm(clock,
reset,
sigma_a,
sigma_b,
sigma_c,
Fn,
dw_x,
dw_y,
dw_z,
dt,
Fn_out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] sigma_a;
input [`BITS-1:0] sigma_b;
input [`BITS-1:0] sigma_c;
input [`BITS-1:0] Fn;
input [`BITS-1:0] dw_x;
input [`BITS-1:0] dw_y;
input [`BITS-1:0] dw_z;
input [`BITS-1:0] dt;
- 2022-04-09 23:29:23下载
- 积分:1
-
vhdlsource
用verilog hdl编写的一些例程,包括加法器/减法器等等,例子较多就不一一列举了(Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the)
- 2007-11-30 15:56:27下载
- 积分:1
-
useful
FPGA做VGA视频显示的详细资料,我找了很久才收集起的,有四篇文章,很有用(FPGA do VGA video display detailed information, I found a long time before they start collecting, with four articles, very useful)
- 2020-12-21 18:29:09下载
- 积分:1
-
FPGA_emif
接口模块,通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块,每个功能模块具有一个带FIFO的输出口和13个独立的可由DSP读写的寄存器,寄存器功能可自定义。模块还包含两个全局寄存器,可实现全局复位,中断等功能。该模块以应用于实际的项目中,目前运行良好(FPGA to emif)
- 2020-12-04 10:59:26下载
- 积分:1
-
hidejj
实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
- 2017-08-02 14:23:12下载
- 积分:1
-
RS_DesignNote
Reed-solomon decoder, encoder design note
- 2010-08-16 09:16:04下载
- 积分:1
-
HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号,在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯,数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分:1