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myuart
使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)
- 2013-07-25 11:45:57下载
- 积分：1
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LDPC_DVB-T2
LDPC encoding code in 1/2code rate for DVB-T2
- 2014-03-11 08:05:18下载
- 积分：1
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attachments_2010_01_29
dct and idct vhdl code
- 2010-03-24 23:08:41下载
- 积分：1
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fir_verilog_matlab
本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)
- 2014-03-21 09:58:41下载
- 积分：1
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encode_64_66
自编的64B/66B编码程序，下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)
- 2011-08-27 10:38:53下载
- 积分：1
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CPU课程设计报告
题目来源于学校的课题系统硬件综合设计，代码中有单周期CPU设计，多周期流水线CPU设计，使用的是Verilog语言，多周期的是基于MIPS架构。
- 2022-05-30 09:34:29下载
- 积分：1
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FIFO
Simulation and Synthesis Techniques for Asynchronous
FIFO Design
- 2013-08-27 16:07:08下载
- 积分：1
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AHB_UVC_and_AHB_IC_Verificat
ahb uvc is an on chip communication protocol for high speed integration and low power utilities performance protocols widely used in all vip applications
- 2020-10-21 12:07:24下载
- 积分：1
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ADPCM
说明： APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)
- 2009-08-22 10:07:03下载
- 积分：1
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Poiseuille---BANFANTAN
格子玻尔兹曼方法模拟poiseuille流，半反弹边界，适合进阶学者(Lattice Boltzmann Simulation poiseuille stream, half rebound border for advanced scholars)
- 2021-04-07 13:29:01下载
- 积分：1
