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CORDIC_ATAN
FPGA实现反正切功能,工程原件,包括测试文件,能够很好实现该功能(FPGA implements arctangent function, original engineering)
- 2018-11-06 15:25:26下载
- 积分:1
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This is what I found online vhdl language used to write the sdram controller cod...
这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱:wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
- 2022-03-26 03:30:04下载
- 积分:1
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AMBA-Bus_Verilog_Model
说明: 该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。(This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.)
- 2021-04-25 21:48:46下载
- 积分:1
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AD9117芯片配置程序
说明: 实现AD9117芯片的配置功能,这是一款DAC芯片(Realize the configuration function of ad9117 chip, which is a DAC chip)
- 2020-07-07 16:58:58下载
- 积分:1
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FPGA verilog代码
说明: 数电实验FPGA verilog代码,包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)
- 2020-04-29 11:16:05下载
- 积分:1
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sound_ranging
改VHDL代码可以实现超声波测距的功能,其精确度达到US级,可以用七段数码管显示其数值(sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging )
- 2014-06-13 20:42:03下载
- 积分:1
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用FPGA实现数字锁相环,开发环境为ISE
用FPGA实现数字锁相环,开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
- 2022-06-22 05:34:34下载
- 积分:1
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The_entire_FPGA_design_flow_Modelsim_Synplify
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)
- 2009-04-06 10:12:48下载
- 积分:1
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cpu
用全加器设计8位运算器逻辑电路图
2、根据逻辑电路用 VHDL编程实现
3、调试编译通过后,仿真
(this file can help you learn the design of cpu)
- 2010-01-05 09:56:11下载
- 积分:1
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FPGA基于VHDL的Turbo码
如果本版权声明未从文件中删除,并且任何衍生作品包含原始版权声明和相关免责声明,则可以不受限制地使用和分发本源文件。
- 2022-03-06 11:21:33下载
- 积分:1