登录
首页 » VHDL » 应用VHDL语言将高稳晶振分频得到1pps,使用GPS的1pps信号作为触发...

应用VHDL语言将高稳晶振分频得到1pps,使用GPS的1pps信号作为触发...

于 2022-05-12 发布 文件大小:34.14 kB
0 250
下载积分: 2 下载次数: 1

代码说明:

应用VHDL语言将高稳晶振分频得到1pps,使用GPS的1pps信号作为触发-Application of VHDL language high stability crystal oscillator frequency to be 1pps, the use of GPS signals as a trigger of 1pps

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • seven_persons
    自己写的7人表决器的verilog程序,实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)
    2013-08-10 07:15:06下载
    积分:1
  • 可编程逻辑器件cpld与单片机双向通信的源程序
    可编程逻辑器件cpld与单片机双向通信的源程序-Programmable logic device CPLD and MCU for two-way communication of the source
    2022-01-25 20:21:15下载
    积分:1
  • tcp/ip master
    tcp/ip master tcp/ip master tcp/ip master tcp/ip master tcp/ip master tcp/ip master
    2023-07-08 00:40:03下载
    积分:1
  • 通信协议AHB_LITE
    AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)
    2020-12-15 10:09:14下载
    积分:1
  • DDS-Waveform-generator
    采用FPGA实现的DDS波形发生器源码,可以实现频率幅值变换、正弦波、方波、三角波输出,输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)
    2012-06-29 23:20:58下载
    积分:1
  • DDC_Ver1.0
    数字下变频(DDC)在如今基于软件无线电的架构中对系统的整体性能决定性的影响,代码为基于Matlab的4通道DDC程序,程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)
    2010-08-04 18:33:14下载
    积分:1
  • verilogsram
    SRAM 读写实验,SRAM存储器的读写操作,Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)
    2017-04-20 22:20:05下载
    积分:1
  • BISS-B---Stimulate_OK
    BISS-B 源代码。包含传感器模式和寄存器模式(BISS-B source code. Includes sensor mode and register mode)
    2021-03-15 19:29:22下载
    积分:1
  • 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考....
    本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
    2022-06-29 06:12:54下载
    积分:1
  • 光栅尺的四细分和辩向电路,并具有计数器功能,利用Quartus综合,可以参考...
    光栅尺的四细分和辩向电路,并具有计数器功能,利用Quartus综合,可以参考-Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to
    2022-04-20 02:09:46下载
    积分:1
  • 696518资源总数
  • 105547会员总数
  • 4今日下载