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Modelsim_SDRAM
本实例用于SDRAM完成读写功能:
先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。(The examples for SDRAM read and write functions.)
- 2013-02-06 10:38:14下载
- 积分：1
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ad73311
AD73311芯片的控制和数据程序，用于控制音频AD芯片。(AD73311 chip control and data program)
- 2021-02-01 23:20:00下载
- 积分：1
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基于Verilog的CRC算法源代码
基于Verilog的CRC算法源代码，基于Verilog的CRC算法源代码，基于Verilog的CRC算法源代码，基于Verilog的CRC算法源代码，基于Verilog的CRC算法源代码，
- 2022-07-14 09:23:30下载
- 积分：1
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vga
利用FPGA控制VGA显示器显示字符汉字的程序，里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)
- 2013-11-25 11:59:13下载
- 积分：1
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McBSP
CPLD对mcbsp的收发操作，占用资源很少(CPLD to mcbsp transceiver operation, small footprint)
- 2011-09-14 16:19:51下载
- 积分：1
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code
Due to its high modularity and carry-free addition, a redundant
binary (RB) representation can be used when designing high performance
multipliers. The conventional RB multiplier requires an additional RB partial
product (RBPP) row, because an error-correcting word (ECW) is generated
by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.
This incurs in an additional RBPP accumulation stage for the MBE multiplier.
In this paper, a new RB modified partial product generator (RBMPPG) is
proposed; it removes the extra ECW and hence, it saves one RBPP
accumulation stage.
- 2017-10-01 23:34:56下载
- 积分：1
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freq_meter
使用verilog写的频率计，可切换档位(Frequency counter using verilog write switch stalls)
- 2012-12-08 00:54:56下载
- 积分：1
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fsk
基于FPGA的fsk调制程序，包括载波的生成，nco的设置(FPGA-based fsk modulation procedures, including carrier generation, nco settings)
- 2016-05-12 21:00:56下载
- 积分：1
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AXI slave
一个AXI slave的Verilog实现代码，内部有基于UVM编写的testbench,该slave是基于AXI3协议来实现的，可以给初学者一些启示
- 2023-09-07 19:50:05下载
- 积分：1
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day8_alu_design
this is verilog code for designing ALU in fpga.
- 2014-05-29 00:19:27下载
- 积分：1
