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vc707-ucf-xdc-rdf0155-rev2-0
vc707 board ucf xdc files
- 2018-06-14 05:50:36下载
- 积分:1
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Verilog串口UART程序
网上关于RS-232的异步收发介绍得很多,最近没事学着摸索用ModelSim来做时序仿真,就结合网上的参考资料和自己的琢磨,做了这个东西。
- 2022-01-26 07:33:30下载
- 积分:1
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dct
基于FPGA的图像压缩算法程序,自己写的,可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)
- 2011-10-23 00:54:17下载
- 积分:1
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Continuous_delay_control_Farrow
说明: matlab代码,利用Farrow结构设计分数延时滤波器,滤波器阶数和个数可分别进行设置,利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
- 2019-06-14 09:10:59下载
- 积分:1
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binary_adder_subtractor
binary adder / subtracter in vhdl
- 2012-12-10 14:54:57下载
- 积分:1
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qianzhaowang
说明: 一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP,实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)
- 2019-01-21 17:18:13下载
- 积分:1
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PL_2FSK
基于VHDl的2FSK调制!用的是altera的quartus11软件(Based on VHDl the 2FSK modulation)
- 2012-12-13 17:20:54下载
- 积分:1
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bignum
a big number class and a calculator using the class
- 2012-12-25 10:14:31下载
- 积分:1
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multiplier_interface
verilog 写的工程,是个基于流水线的乘法器(verilog write the works, is based on a pipelined multiplier)
- 2012-09-21 10:04:54下载
- 积分:1
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freq
vhdl八位十进制数字频率计的设计,顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)
- 2012-10-09 15:09:22下载
- 积分:1